403-net-mvneta-convert-to-phylink.patch 29 KB

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  1. From 36f29e6cf8071fed3854d9825217ed2a3c83b990 Mon Sep 17 00:00:00 2001
  2. From: Russell King <[email protected]>
  3. Date: Wed, 16 Sep 2015 21:27:10 +0100
  4. Subject: net: mvneta: convert to phylink
  5. Convert mvneta to use phylink, which models the MAC to PHY link in
  6. a generic, reusable form.
  7. Signed-off-by: Russell King <[email protected]>
  8. - remove unused sync status
  9. ---
  10. drivers/net/ethernet/marvell/Kconfig | 2 +-
  11. drivers/net/ethernet/marvell/mvneta.c | 594 ++++++++++++++++++++--------------
  12. 2 files changed, 349 insertions(+), 247 deletions(-)
  13. --- a/drivers/net/ethernet/marvell/Kconfig
  14. +++ b/drivers/net/ethernet/marvell/Kconfig
  15. @@ -60,7 +60,7 @@ config MVNETA
  16. depends on ARCH_MVEBU || COMPILE_TEST
  17. depends on HAS_DMA
  18. select MVMDIO
  19. - select FIXED_PHY
  20. + select PHYLINK
  21. ---help---
  22. This driver supports the network interface units in the
  23. Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
  24. --- a/drivers/net/ethernet/marvell/mvneta.c
  25. +++ b/drivers/net/ethernet/marvell/mvneta.c
  26. @@ -28,7 +28,7 @@
  27. #include <linux/of_mdio.h>
  28. #include <linux/of_net.h>
  29. #include <linux/phy.h>
  30. -#include <linux/phy_fixed.h>
  31. +#include <linux/phylink.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/skbuff.h>
  34. #include <net/hwbm.h>
  35. @@ -189,6 +189,7 @@
  36. #define MVNETA_GMAC_CTRL_0 0x2c00
  37. #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
  38. #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  39. +#define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
  40. #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
  41. #define MVNETA_GMAC_CTRL_2 0x2c08
  42. #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
  43. @@ -204,13 +205,19 @@
  44. #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
  45. #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
  46. #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
  47. +#define MVNETA_GMAC_AN_COMPLETE BIT(11)
  48. +#define MVNETA_GMAC_SYNC_OK BIT(14)
  49. #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
  50. #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
  51. #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
  52. #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
  53. +#define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
  54. +#define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
  55. #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
  56. #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
  57. #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
  58. +#define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
  59. +#define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
  60. #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
  61. #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  62. #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
  63. @@ -237,6 +244,12 @@
  64. #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
  65. #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  66. +#define MVNETA_LPI_CTRL_0 0x2cc0
  67. +#define MVNETA_LPI_CTRL_1 0x2cc4
  68. +#define MVNETA_LPI_REQUEST_ENABLE BIT(0)
  69. +#define MVNETA_LPI_CTRL_2 0x2cc8
  70. +#define MVNETA_LPI_STATUS 0x2ccc
  71. +
  72. #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
  73. /* Descriptor ring Macros */
  74. @@ -313,6 +326,11 @@
  75. #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
  76. (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
  77. +enum {
  78. + ETHTOOL_STAT_EEE_WAKEUP,
  79. + ETHTOOL_MAX_STATS,
  80. +};
  81. +
  82. struct mvneta_statistic {
  83. unsigned short offset;
  84. unsigned short type;
  85. @@ -321,6 +339,7 @@ struct mvneta_statistic {
  86. #define T_REG_32 32
  87. #define T_REG_64 64
  88. +#define T_SW 1
  89. static const struct mvneta_statistic mvneta_statistics[] = {
  90. { 0x3000, T_REG_64, "good_octets_received", },
  91. @@ -355,6 +374,7 @@ static const struct mvneta_statistic mvn
  92. { 0x304c, T_REG_32, "broadcast_frames_sent", },
  93. { 0x3054, T_REG_32, "fc_sent", },
  94. { 0x300c, T_REG_32, "internal_mac_transmit_err", },
  95. + { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", },
  96. };
  97. struct mvneta_pcpu_stats {
  98. @@ -407,20 +427,19 @@ struct mvneta_port {
  99. u16 tx_ring_size;
  100. u16 rx_ring_size;
  101. - struct mii_bus *mii_bus;
  102. - phy_interface_t phy_interface;
  103. - struct device_node *phy_node;
  104. - unsigned int link;
  105. - unsigned int duplex;
  106. - unsigned int speed;
  107. + struct device_node *dn;
  108. unsigned int tx_csum_limit;
  109. - unsigned int use_inband_status:1;
  110. + struct phylink *phylink;
  111. struct mvneta_bm *bm_priv;
  112. struct mvneta_bm_pool *pool_long;
  113. struct mvneta_bm_pool *pool_short;
  114. int bm_win_id;
  115. + bool eee_enabled;
  116. + bool eee_active;
  117. + bool tx_lpi_enabled;
  118. +
  119. u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
  120. u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
  121. @@ -1215,10 +1234,6 @@ static void mvneta_port_disable(struct m
  122. val &= ~MVNETA_GMAC0_PORT_ENABLE;
  123. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  124. - pp->link = 0;
  125. - pp->duplex = -1;
  126. - pp->speed = 0;
  127. -
  128. udelay(200);
  129. }
  130. @@ -1278,44 +1293,6 @@ static void mvneta_set_other_mcast_table
  131. mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
  132. }
  133. -static void mvneta_set_autoneg(struct mvneta_port *pp, int enable)
  134. -{
  135. - u32 val;
  136. -
  137. - if (enable) {
  138. - val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  139. - val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
  140. - MVNETA_GMAC_FORCE_LINK_DOWN |
  141. - MVNETA_GMAC_AN_FLOW_CTRL_EN);
  142. - val |= MVNETA_GMAC_INBAND_AN_ENABLE |
  143. - MVNETA_GMAC_AN_SPEED_EN |
  144. - MVNETA_GMAC_AN_DUPLEX_EN;
  145. - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  146. -
  147. - val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
  148. - val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
  149. - mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
  150. -
  151. - val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
  152. - val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
  153. - mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
  154. - } else {
  155. - val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  156. - val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
  157. - MVNETA_GMAC_AN_SPEED_EN |
  158. - MVNETA_GMAC_AN_DUPLEX_EN);
  159. - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  160. -
  161. - val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
  162. - val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
  163. - mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
  164. -
  165. - val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
  166. - val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
  167. - mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
  168. - }
  169. -}
  170. -
  171. static void mvneta_percpu_unmask_interrupt(void *arg)
  172. {
  173. struct mvneta_port *pp = arg;
  174. @@ -1468,7 +1445,6 @@ static void mvneta_defaults_set(struct m
  175. val &= ~MVNETA_PHY_POLLING_ENABLE;
  176. mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
  177. - mvneta_set_autoneg(pp, pp->use_inband_status);
  178. mvneta_set_ucast_table(pp, -1);
  179. mvneta_set_special_mcast_table(pp, -1);
  180. mvneta_set_other_mcast_table(pp, -1);
  181. @@ -2693,26 +2669,11 @@ static irqreturn_t mvneta_percpu_isr(int
  182. return IRQ_HANDLED;
  183. }
  184. -static int mvneta_fixed_link_update(struct mvneta_port *pp,
  185. - struct phy_device *phy)
  186. +static void mvneta_link_change(struct mvneta_port *pp)
  187. {
  188. - struct fixed_phy_status status;
  189. - struct fixed_phy_status changed = {};
  190. u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
  191. - status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
  192. - if (gmac_stat & MVNETA_GMAC_SPEED_1000)
  193. - status.speed = SPEED_1000;
  194. - else if (gmac_stat & MVNETA_GMAC_SPEED_100)
  195. - status.speed = SPEED_100;
  196. - else
  197. - status.speed = SPEED_10;
  198. - status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
  199. - changed.link = 1;
  200. - changed.speed = 1;
  201. - changed.duplex = 1;
  202. - fixed_phy_update_state(phy, &status, &changed);
  203. - return 0;
  204. + phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
  205. }
  206. /* NAPI handler
  207. @@ -2728,7 +2689,6 @@ static int mvneta_poll(struct napi_struc
  208. u32 cause_rx_tx;
  209. int rx_queue;
  210. struct mvneta_port *pp = netdev_priv(napi->dev);
  211. - struct net_device *ndev = pp->dev;
  212. struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
  213. if (!netif_running(pp->dev)) {
  214. @@ -2742,12 +2702,11 @@ static int mvneta_poll(struct napi_struc
  215. u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
  216. mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
  217. - if (pp->use_inband_status && (cause_misc &
  218. - (MVNETA_CAUSE_PHY_STATUS_CHANGE |
  219. - MVNETA_CAUSE_LINK_CHANGE |
  220. - MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
  221. - mvneta_fixed_link_update(pp, ndev->phydev);
  222. - }
  223. +
  224. + if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
  225. + MVNETA_CAUSE_LINK_CHANGE |
  226. + MVNETA_CAUSE_PSC_SYNC_CHANGE))
  227. + mvneta_link_change(pp);
  228. }
  229. /* Release Tx descriptors */
  230. @@ -3061,7 +3020,6 @@ static int mvneta_setup_txqs(struct mvne
  231. static void mvneta_start_dev(struct mvneta_port *pp)
  232. {
  233. int cpu;
  234. - struct net_device *ndev = pp->dev;
  235. mvneta_max_rx_size_set(pp, pp->pkt_size);
  236. mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
  237. @@ -3089,16 +3047,15 @@ static void mvneta_start_dev(struct mvne
  238. MVNETA_CAUSE_LINK_CHANGE |
  239. MVNETA_CAUSE_PSC_SYNC_CHANGE);
  240. - phy_start(ndev->phydev);
  241. + phylink_start(pp->phylink);
  242. netif_tx_start_all_queues(pp->dev);
  243. }
  244. static void mvneta_stop_dev(struct mvneta_port *pp)
  245. {
  246. unsigned int cpu;
  247. - struct net_device *ndev = pp->dev;
  248. - phy_stop(ndev->phydev);
  249. + phylink_stop(pp->phylink);
  250. if (!pp->neta_armada3700) {
  251. for_each_online_cpu(cpu) {
  252. @@ -3252,103 +3209,232 @@ static int mvneta_set_mac_addr(struct ne
  253. return 0;
  254. }
  255. -static void mvneta_adjust_link(struct net_device *ndev)
  256. +static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
  257. + struct phylink_link_state *state)
  258. +{
  259. + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
  260. +
  261. + /* Allow all the expected bits */
  262. + phylink_set(mask, Autoneg);
  263. + phylink_set_port_modes(mask);
  264. +
  265. + /* Asymmetric pause is unsupported */
  266. + phylink_set(mask, Pause);
  267. + /* Half-duplex at speeds higher than 100Mbit is unsupported */
  268. + phylink_set(mask, 1000baseT_Full);
  269. + phylink_set(mask, 1000baseX_Full);
  270. +
  271. + if (state->interface != PHY_INTERFACE_MODE_1000BASEX) {
  272. + /* 10M and 100M are only supported in non-802.3z mode */
  273. + phylink_set(mask, 10baseT_Half);
  274. + phylink_set(mask, 10baseT_Full);
  275. + phylink_set(mask, 100baseT_Half);
  276. + phylink_set(mask, 100baseT_Full);
  277. + }
  278. +
  279. + bitmap_and(supported, supported, mask,
  280. + __ETHTOOL_LINK_MODE_MASK_NBITS);
  281. + bitmap_and(state->advertising, state->advertising, mask,
  282. + __ETHTOOL_LINK_MODE_MASK_NBITS);
  283. +}
  284. +
  285. +static int mvneta_mac_link_state(struct net_device *ndev,
  286. + struct phylink_link_state *state)
  287. {
  288. struct mvneta_port *pp = netdev_priv(ndev);
  289. - struct phy_device *phydev = ndev->phydev;
  290. - int status_change = 0;
  291. + u32 gmac_stat;
  292. - if (phydev->link) {
  293. - if ((pp->speed != phydev->speed) ||
  294. - (pp->duplex != phydev->duplex)) {
  295. - u32 val;
  296. -
  297. - val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  298. - val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
  299. - MVNETA_GMAC_CONFIG_GMII_SPEED |
  300. - MVNETA_GMAC_CONFIG_FULL_DUPLEX);
  301. -
  302. - if (phydev->duplex)
  303. - val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  304. -
  305. - if (phydev->speed == SPEED_1000)
  306. - val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  307. - else if (phydev->speed == SPEED_100)
  308. - val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  309. + gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
  310. - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  311. + if (gmac_stat & MVNETA_GMAC_SPEED_1000)
  312. + state->speed = SPEED_1000;
  313. + else if (gmac_stat & MVNETA_GMAC_SPEED_100)
  314. + state->speed = SPEED_100;
  315. + else
  316. + state->speed = SPEED_10;
  317. - pp->duplex = phydev->duplex;
  318. - pp->speed = phydev->speed;
  319. - }
  320. + state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
  321. + state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
  322. + state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
  323. +
  324. + state->pause = 0;
  325. + if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
  326. + state->pause |= MLO_PAUSE_RX;
  327. + if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
  328. + state->pause |= MLO_PAUSE_TX;
  329. +
  330. + return 1;
  331. +}
  332. +
  333. +static void mvneta_mac_an_restart(struct net_device *ndev)
  334. +{
  335. + struct mvneta_port *pp = netdev_priv(ndev);
  336. + u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  337. +
  338. + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
  339. + gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
  340. + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
  341. + gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
  342. +}
  343. +
  344. +static void mvneta_mac_config(struct net_device *ndev, unsigned int mode,
  345. + const struct phylink_link_state *state)
  346. +{
  347. + struct mvneta_port *pp = netdev_priv(ndev);
  348. + u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  349. + u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
  350. + u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
  351. + u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  352. +
  353. + new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
  354. + new_ctrl2 = gmac_ctrl2 & ~MVNETA_GMAC2_INBAND_AN_ENABLE;
  355. + new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
  356. + new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
  357. + MVNETA_GMAC_INBAND_RESTART_AN |
  358. + MVNETA_GMAC_CONFIG_MII_SPEED |
  359. + MVNETA_GMAC_CONFIG_GMII_SPEED |
  360. + MVNETA_GMAC_AN_SPEED_EN |
  361. + MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL |
  362. + MVNETA_GMAC_CONFIG_FLOW_CTRL |
  363. + MVNETA_GMAC_AN_FLOW_CTRL_EN |
  364. + MVNETA_GMAC_CONFIG_FULL_DUPLEX |
  365. + MVNETA_GMAC_AN_DUPLEX_EN);
  366. +
  367. + if (phylink_test(state->advertising, Pause))
  368. + new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
  369. + if (state->pause & MLO_PAUSE_TXRX_MASK)
  370. + new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
  371. +
  372. + if (!phylink_autoneg_inband(mode)) {
  373. + /* Phy or fixed speed */
  374. + if (state->duplex)
  375. + new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  376. +
  377. + if (state->speed == SPEED_1000)
  378. + new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  379. + else if (state->speed == SPEED_100)
  380. + new_an |= MVNETA_GMAC_CONFIG_MII_SPEED;
  381. + } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
  382. + /* SGMII mode receives the state from the PHY */
  383. + new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
  384. + new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
  385. + new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
  386. + MVNETA_GMAC_FORCE_LINK_PASS)) |
  387. + MVNETA_GMAC_INBAND_AN_ENABLE |
  388. + MVNETA_GMAC_AN_SPEED_EN |
  389. + MVNETA_GMAC_AN_DUPLEX_EN;
  390. + } else {
  391. + /* 802.3z negotiation - only 1000base-X */
  392. + new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
  393. + new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
  394. + new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
  395. + MVNETA_GMAC_FORCE_LINK_PASS)) |
  396. + MVNETA_GMAC_INBAND_AN_ENABLE |
  397. + MVNETA_GMAC_CONFIG_GMII_SPEED |
  398. + /* The MAC only supports FD mode */
  399. + MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  400. +
  401. + if (state->pause & MLO_PAUSE_AN && state->an_enabled)
  402. + new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
  403. + }
  404. +
  405. + /* Armada 370 documentation says we can only change the port mode
  406. + * and in-band enable when the link is down, so force it down
  407. + * while making these changes. We also do this for GMAC_CTRL2 */
  408. + if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
  409. + (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
  410. + (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
  411. + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
  412. + (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) |
  413. + MVNETA_GMAC_FORCE_LINK_DOWN);
  414. + }
  415. +
  416. + if (new_ctrl0 != gmac_ctrl0)
  417. + mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
  418. + if (new_ctrl2 != gmac_ctrl2)
  419. + mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
  420. + if (new_clk != gmac_clk)
  421. + mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
  422. + if (new_an != gmac_an)
  423. + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
  424. +}
  425. +
  426. +static void mvneta_set_eee(struct mvneta_port *pp, bool enable)
  427. +{
  428. + u32 lpi_ctl1;
  429. +
  430. + lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
  431. + if (enable)
  432. + lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE;
  433. + else
  434. + lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE;
  435. + mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1);
  436. +}
  437. +
  438. +static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode)
  439. +{
  440. + struct mvneta_port *pp = netdev_priv(ndev);
  441. + u32 val;
  442. +
  443. + mvneta_port_down(pp);
  444. +
  445. + if (!phylink_autoneg_inband(mode)) {
  446. + val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  447. + val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
  448. + val |= MVNETA_GMAC_FORCE_LINK_DOWN;
  449. + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  450. }
  451. - if (phydev->link != pp->link) {
  452. - if (!phydev->link) {
  453. - pp->duplex = -1;
  454. - pp->speed = 0;
  455. - }
  456. + pp->eee_active = false;
  457. + mvneta_set_eee(pp, false);
  458. +}
  459. +
  460. +static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode,
  461. + struct phy_device *phy)
  462. +{
  463. + struct mvneta_port *pp = netdev_priv(ndev);
  464. + u32 val;
  465. - pp->link = phydev->link;
  466. - status_change = 1;
  467. + if (!phylink_autoneg_inband(mode)) {
  468. + val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  469. + val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
  470. + val |= MVNETA_GMAC_FORCE_LINK_PASS;
  471. + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  472. }
  473. - if (status_change) {
  474. - if (phydev->link) {
  475. - if (!pp->use_inband_status) {
  476. - u32 val = mvreg_read(pp,
  477. - MVNETA_GMAC_AUTONEG_CONFIG);
  478. - val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
  479. - val |= MVNETA_GMAC_FORCE_LINK_PASS;
  480. - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
  481. - val);
  482. - }
  483. - mvneta_port_up(pp);
  484. - } else {
  485. - if (!pp->use_inband_status) {
  486. - u32 val = mvreg_read(pp,
  487. - MVNETA_GMAC_AUTONEG_CONFIG);
  488. - val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
  489. - val |= MVNETA_GMAC_FORCE_LINK_DOWN;
  490. - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
  491. - val);
  492. - }
  493. - mvneta_port_down(pp);
  494. - }
  495. - phy_print_status(phydev);
  496. + mvneta_port_up(pp);
  497. +
  498. + if (phy && pp->eee_enabled) {
  499. + pp->eee_active = phy_init_eee(phy, 0) >= 0;
  500. + mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled);
  501. }
  502. }
  503. +static const struct phylink_mac_ops mvneta_phylink_ops = {
  504. + .validate = mvneta_validate,
  505. + .mac_link_state = mvneta_mac_link_state,
  506. + .mac_an_restart = mvneta_mac_an_restart,
  507. + .mac_config = mvneta_mac_config,
  508. + .mac_link_down = mvneta_mac_link_down,
  509. + .mac_link_up = mvneta_mac_link_up,
  510. +};
  511. +
  512. static int mvneta_mdio_probe(struct mvneta_port *pp)
  513. {
  514. - struct phy_device *phy_dev;
  515. struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
  516. + int err = phylink_of_phy_connect(pp->phylink, pp->dn);
  517. + if (err)
  518. + netdev_err(pp->dev, "could not attach PHY\n");
  519. - phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
  520. - pp->phy_interface);
  521. - if (!phy_dev) {
  522. - netdev_err(pp->dev, "could not find the PHY\n");
  523. - return -ENODEV;
  524. - }
  525. -
  526. - phy_ethtool_get_wol(phy_dev, &wol);
  527. + phylink_ethtool_get_wol(pp->phylink, &wol);
  528. device_set_wakeup_capable(&pp->dev->dev, !!wol.supported);
  529. - phy_dev->supported &= PHY_GBIT_FEATURES;
  530. - phy_dev->advertising = phy_dev->supported;
  531. -
  532. - pp->link = 0;
  533. - pp->duplex = 0;
  534. - pp->speed = 0;
  535. -
  536. - return 0;
  537. + return err;
  538. }
  539. static void mvneta_mdio_remove(struct mvneta_port *pp)
  540. {
  541. - struct net_device *ndev = pp->dev;
  542. -
  543. - phy_disconnect(ndev->phydev);
  544. + phylink_disconnect_phy(pp->phylink);
  545. }
  546. /* Electing a CPU must be done in an atomic way: it should be done
  547. @@ -3627,10 +3713,9 @@ static int mvneta_stop(struct net_device
  548. static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  549. {
  550. - if (!dev->phydev)
  551. - return -ENOTSUPP;
  552. + struct mvneta_port *pp = netdev_priv(dev);
  553. - return phy_mii_ioctl(dev->phydev, ifr, cmd);
  554. + return phylink_mii_ioctl(pp->phylink, ifr, cmd);
  555. }
  556. /* Ethtool methods */
  557. @@ -3641,44 +3726,25 @@ mvneta_ethtool_set_link_ksettings(struct
  558. const struct ethtool_link_ksettings *cmd)
  559. {
  560. struct mvneta_port *pp = netdev_priv(ndev);
  561. - struct phy_device *phydev = ndev->phydev;
  562. - if (!phydev)
  563. - return -ENODEV;
  564. -
  565. - if ((cmd->base.autoneg == AUTONEG_ENABLE) != pp->use_inband_status) {
  566. - u32 val;
  567. -
  568. - mvneta_set_autoneg(pp, cmd->base.autoneg == AUTONEG_ENABLE);
  569. -
  570. - if (cmd->base.autoneg == AUTONEG_DISABLE) {
  571. - val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  572. - val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
  573. - MVNETA_GMAC_CONFIG_GMII_SPEED |
  574. - MVNETA_GMAC_CONFIG_FULL_DUPLEX);
  575. -
  576. - if (phydev->duplex)
  577. - val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  578. + return phylink_ethtool_ksettings_set(pp->phylink, cmd);
  579. +}
  580. - if (phydev->speed == SPEED_1000)
  581. - val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  582. - else if (phydev->speed == SPEED_100)
  583. - val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  584. +/* Get link ksettings for ethtools */
  585. +static int
  586. +mvneta_ethtool_get_link_ksettings(struct net_device *ndev,
  587. + struct ethtool_link_ksettings *cmd)
  588. +{
  589. + struct mvneta_port *pp = netdev_priv(ndev);
  590. - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  591. - }
  592. + return phylink_ethtool_ksettings_get(pp->phylink, cmd);
  593. +}
  594. - pp->use_inband_status = (cmd->base.autoneg == AUTONEG_ENABLE);
  595. - netdev_info(pp->dev, "autoneg status set to %i\n",
  596. - pp->use_inband_status);
  597. -
  598. - if (netif_running(ndev)) {
  599. - mvneta_port_down(pp);
  600. - mvneta_port_up(pp);
  601. - }
  602. - }
  603. +static int mvneta_ethtool_nway_reset(struct net_device *dev)
  604. +{
  605. + struct mvneta_port *pp = netdev_priv(dev);
  606. - return phy_ethtool_ksettings_set(ndev->phydev, cmd);
  607. + return phylink_ethtool_nway_reset(pp->phylink);
  608. }
  609. /* Set interrupt coalescing for ethtools */
  610. @@ -3770,6 +3836,22 @@ static int mvneta_ethtool_set_ringparam(
  611. return 0;
  612. }
  613. +static void mvneta_ethtool_get_pauseparam(struct net_device *dev,
  614. + struct ethtool_pauseparam *pause)
  615. +{
  616. + struct mvneta_port *pp = netdev_priv(dev);
  617. +
  618. + phylink_ethtool_get_pauseparam(pp->phylink, pause);
  619. +}
  620. +
  621. +static int mvneta_ethtool_set_pauseparam(struct net_device *dev,
  622. + struct ethtool_pauseparam *pause)
  623. +{
  624. + struct mvneta_port *pp = netdev_priv(dev);
  625. +
  626. + return phylink_ethtool_set_pauseparam(pp->phylink, pause);
  627. +}
  628. +
  629. static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
  630. u8 *data)
  631. {
  632. @@ -3786,26 +3868,35 @@ static void mvneta_ethtool_update_stats(
  633. {
  634. const struct mvneta_statistic *s;
  635. void __iomem *base = pp->base;
  636. - u32 high, low, val;
  637. - u64 val64;
  638. + u32 high, low;
  639. + u64 val;
  640. int i;
  641. for (i = 0, s = mvneta_statistics;
  642. s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
  643. s++, i++) {
  644. + val = 0;
  645. +
  646. switch (s->type) {
  647. case T_REG_32:
  648. val = readl_relaxed(base + s->offset);
  649. - pp->ethtool_stats[i] += val;
  650. break;
  651. case T_REG_64:
  652. /* Docs say to read low 32-bit then high */
  653. low = readl_relaxed(base + s->offset);
  654. high = readl_relaxed(base + s->offset + 4);
  655. - val64 = (u64)high << 32 | low;
  656. - pp->ethtool_stats[i] += val64;
  657. + val = (u64)high << 32 | low;
  658. + break;
  659. + case T_SW:
  660. + switch (s->offset) {
  661. + case ETHTOOL_STAT_EEE_WAKEUP:
  662. + val = phylink_get_eee_err(pp->phylink);
  663. + break;
  664. + }
  665. break;
  666. }
  667. +
  668. + pp->ethtool_stats[i] += val;
  669. }
  670. }
  671. @@ -3940,28 +4031,65 @@ static int mvneta_ethtool_get_rxfh(struc
  672. static void mvneta_ethtool_get_wol(struct net_device *dev,
  673. struct ethtool_wolinfo *wol)
  674. {
  675. - wol->supported = 0;
  676. - wol->wolopts = 0;
  677. + struct mvneta_port *pp = netdev_priv(dev);
  678. - if (dev->phydev)
  679. - phy_ethtool_get_wol(dev->phydev, wol);
  680. + phylink_ethtool_get_wol(pp->phylink, wol);
  681. }
  682. static int mvneta_ethtool_set_wol(struct net_device *dev,
  683. struct ethtool_wolinfo *wol)
  684. {
  685. + struct mvneta_port *pp = netdev_priv(dev);
  686. int ret;
  687. - if (!dev->phydev)
  688. - return -EOPNOTSUPP;
  689. -
  690. - ret = phy_ethtool_set_wol(dev->phydev, wol);
  691. + ret = phylink_ethtool_set_wol(pp->phylink, wol);
  692. if (!ret)
  693. device_set_wakeup_enable(&dev->dev, !!wol->wolopts);
  694. return ret;
  695. }
  696. +static int mvneta_ethtool_get_eee(struct net_device *dev,
  697. + struct ethtool_eee *eee)
  698. +{
  699. + struct mvneta_port *pp = netdev_priv(dev);
  700. + u32 lpi_ctl0;
  701. +
  702. + lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
  703. +
  704. + eee->eee_enabled = pp->eee_enabled;
  705. + eee->eee_active = pp->eee_active;
  706. + eee->tx_lpi_enabled = pp->tx_lpi_enabled;
  707. + eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale;
  708. +
  709. + return phylink_ethtool_get_eee(pp->phylink, eee);
  710. +}
  711. +
  712. +static int mvneta_ethtool_set_eee(struct net_device *dev,
  713. + struct ethtool_eee *eee)
  714. +{
  715. + struct mvneta_port *pp = netdev_priv(dev);
  716. + u32 lpi_ctl0;
  717. +
  718. + /* The Armada 37x documents do not give limits for this other than
  719. + * it being an 8-bit register. */
  720. + if (eee->tx_lpi_enabled &&
  721. + (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255))
  722. + return -EINVAL;
  723. +
  724. + lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
  725. + lpi_ctl0 &= ~(0xff << 8);
  726. + lpi_ctl0 |= eee->tx_lpi_timer << 8;
  727. + mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0);
  728. +
  729. + pp->eee_enabled = eee->eee_enabled;
  730. + pp->tx_lpi_enabled = eee->tx_lpi_enabled;
  731. +
  732. + mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled);
  733. +
  734. + return phylink_ethtool_set_eee(pp->phylink, eee);
  735. +}
  736. +
  737. static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
  738. void *accel_priv,
  739. select_queue_fallback_t fallback)
  740. @@ -3985,13 +4113,15 @@ static const struct net_device_ops mvnet
  741. };
  742. static const struct ethtool_ops mvneta_eth_tool_ops = {
  743. - .nway_reset = phy_ethtool_nway_reset,
  744. + .nway_reset = mvneta_ethtool_nway_reset,
  745. .get_link = ethtool_op_get_link,
  746. .set_coalesce = mvneta_ethtool_set_coalesce,
  747. .get_coalesce = mvneta_ethtool_get_coalesce,
  748. .get_drvinfo = mvneta_ethtool_get_drvinfo,
  749. .get_ringparam = mvneta_ethtool_get_ringparam,
  750. .set_ringparam = mvneta_ethtool_set_ringparam,
  751. + .get_pauseparam = mvneta_ethtool_get_pauseparam,
  752. + .set_pauseparam = mvneta_ethtool_set_pauseparam,
  753. .get_strings = mvneta_ethtool_get_strings,
  754. .get_ethtool_stats = mvneta_ethtool_get_stats,
  755. .get_sset_count = mvneta_ethtool_get_sset_count,
  756. @@ -3999,10 +4129,12 @@ static const struct ethtool_ops mvneta_e
  757. .get_rxnfc = mvneta_ethtool_get_rxnfc,
  758. .get_rxfh = mvneta_ethtool_get_rxfh,
  759. .set_rxfh = mvneta_ethtool_set_rxfh,
  760. - .get_link_ksettings = phy_ethtool_get_link_ksettings,
  761. + .get_link_ksettings = mvneta_ethtool_get_link_ksettings,
  762. .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
  763. .get_wol = mvneta_ethtool_get_wol,
  764. .set_wol = mvneta_ethtool_set_wol,
  765. + .get_eee = mvneta_ethtool_get_eee,
  766. + .set_eee = mvneta_ethtool_set_eee,
  767. };
  768. /* Initialize hw */
  769. @@ -4147,14 +4279,13 @@ static int mvneta_probe(struct platform_
  770. {
  771. struct resource *res;
  772. struct device_node *dn = pdev->dev.of_node;
  773. - struct device_node *phy_node;
  774. struct device_node *bm_node;
  775. struct mvneta_port *pp;
  776. struct net_device *dev;
  777. + struct phylink *phylink;
  778. const char *dt_mac_addr;
  779. char hw_mac_addr[ETH_ALEN];
  780. const char *mac_from;
  781. - const char *managed;
  782. int tx_csum_limit;
  783. int phy_mode;
  784. int err;
  785. @@ -4170,31 +4301,11 @@ static int mvneta_probe(struct platform_
  786. goto err_free_netdev;
  787. }
  788. - phy_node = of_parse_phandle(dn, "phy", 0);
  789. - if (!phy_node) {
  790. - if (!of_phy_is_fixed_link(dn)) {
  791. - dev_err(&pdev->dev, "no PHY specified\n");
  792. - err = -ENODEV;
  793. - goto err_free_irq;
  794. - }
  795. -
  796. - err = of_phy_register_fixed_link(dn);
  797. - if (err < 0) {
  798. - dev_err(&pdev->dev, "cannot register fixed PHY\n");
  799. - goto err_free_irq;
  800. - }
  801. -
  802. - /* In the case of a fixed PHY, the DT node associated
  803. - * to the PHY is the Ethernet MAC DT node.
  804. - */
  805. - phy_node = of_node_get(dn);
  806. - }
  807. -
  808. phy_mode = of_get_phy_mode(dn);
  809. if (phy_mode < 0) {
  810. dev_err(&pdev->dev, "incorrect phy-mode\n");
  811. err = -EINVAL;
  812. - goto err_put_phy_node;
  813. + goto err_free_irq;
  814. }
  815. dev->tx_queue_len = MVNETA_MAX_TXD;
  816. @@ -4205,12 +4316,7 @@ static int mvneta_probe(struct platform_
  817. pp = netdev_priv(dev);
  818. spin_lock_init(&pp->lock);
  819. - pp->phy_node = phy_node;
  820. - pp->phy_interface = phy_mode;
  821. -
  822. - err = of_property_read_string(dn, "managed", &managed);
  823. - pp->use_inband_status = (err == 0 &&
  824. - strcmp(managed, "in-band-status") == 0);
  825. + pp->dn = dn;
  826. pp->rxq_def = rxq_def;
  827. @@ -4232,7 +4338,7 @@ static int mvneta_probe(struct platform_
  828. pp->clk = devm_clk_get(&pdev->dev, NULL);
  829. if (IS_ERR(pp->clk)) {
  830. err = PTR_ERR(pp->clk);
  831. - goto err_put_phy_node;
  832. + goto err_free_irq;
  833. }
  834. clk_prepare_enable(pp->clk);
  835. @@ -4358,6 +4464,14 @@ static int mvneta_probe(struct platform_
  836. /* 9676 == 9700 - 20 and rounding to 8 */
  837. dev->max_mtu = 9676;
  838. + phylink = phylink_create(dev, dn, phy_mode, &mvneta_phylink_ops);
  839. + if (IS_ERR(phylink)) {
  840. + err = PTR_ERR(phylink);
  841. + goto err_free_stats;
  842. + }
  843. +
  844. + pp->phylink = phylink;
  845. +
  846. err = register_netdev(dev);
  847. if (err < 0) {
  848. dev_err(&pdev->dev, "failed to register\n");
  849. @@ -4369,14 +4483,6 @@ static int mvneta_probe(struct platform_
  850. platform_set_drvdata(pdev, pp->dev);
  851. - if (pp->use_inband_status) {
  852. - struct phy_device *phy = of_phy_find_device(dn);
  853. -
  854. - mvneta_fixed_link_update(pp, phy);
  855. -
  856. - put_device(&phy->mdio.dev);
  857. - }
  858. -
  859. return 0;
  860. err_netdev:
  861. @@ -4387,16 +4493,14 @@ err_netdev:
  862. 1 << pp->id);
  863. }
  864. err_free_stats:
  865. + if (pp->phylink)
  866. + phylink_destroy(pp->phylink);
  867. free_percpu(pp->stats);
  868. err_free_ports:
  869. free_percpu(pp->ports);
  870. err_clk:
  871. clk_disable_unprepare(pp->clk_bus);
  872. clk_disable_unprepare(pp->clk);
  873. -err_put_phy_node:
  874. - of_node_put(phy_node);
  875. - if (of_phy_is_fixed_link(dn))
  876. - of_phy_deregister_fixed_link(dn);
  877. err_free_irq:
  878. irq_dispose_mapping(dev->irq);
  879. err_free_netdev:
  880. @@ -4408,7 +4512,6 @@ err_free_netdev:
  881. static int mvneta_remove(struct platform_device *pdev)
  882. {
  883. struct net_device *dev = platform_get_drvdata(pdev);
  884. - struct device_node *dn = pdev->dev.of_node;
  885. struct mvneta_port *pp = netdev_priv(dev);
  886. unregister_netdev(dev);
  887. @@ -4416,10 +4519,8 @@ static int mvneta_remove(struct platform
  888. clk_disable_unprepare(pp->clk);
  889. free_percpu(pp->ports);
  890. free_percpu(pp->stats);
  891. - if (of_phy_is_fixed_link(dn))
  892. - of_phy_deregister_fixed_link(dn);
  893. irq_dispose_mapping(dev->irq);
  894. - of_node_put(pp->phy_node);
  895. + phylink_destroy(pp->phylink);
  896. free_netdev(dev);
  897. if (pp->bm_priv) {
  898. @@ -4471,9 +4572,6 @@ static int mvneta_resume(struct device *
  899. return err;
  900. }
  901. - if (pp->use_inband_status)
  902. - mvneta_fixed_link_update(pp, dev->phydev);
  903. -
  904. netif_device_attach(dev);
  905. if (netif_running(dev)) {
  906. mvneta_open(dev);