openwrt/target/linux/layerscape/files/arch/arm64/boot/dts/freescale/traverse-ls1043s.dts

/*
 * Device Tree Include file for Traverse LS1043S board.
 *
 * Copyright 2014-2015, Freescale Semiconductor
 * Copyright 2017-2018, Traverse Technologies
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "fsl-ls1043a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "Traverse LS1043S";
	compatible = "traverse,ls1043s";

	aliases {
		crypto = &crypto;
		ethernet0 = &EMAC0;
		ethernet1 = &EMAC1;
		ethernet2 = &EMAC2;
		ethernet3 = &EMAC3;
		ethernet4 = &EMAC4;
		ethernet5 = &EMAC5;
	};

	leds {
		compatible = "gpio-leds";
		gpio0 {
			label = "ls1043s:green:user0";
			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
		};
		gpio1 {
			label = "ls1043s:green:user1";
			gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
		};
		/* LED D17 */
		gpio2 {
			label = "ls1043s:green:wan";
			gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
		};
		gpio3 {
			label = "ls1043s:yellow:wan";
			gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
		};
		/* LED D18 */
		gpio4 {
			label = "ls1043s:green:mgmt";
			gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
		};
		gpio5 {
			label = "ls1043s:yellow:mgmt";
			gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
		};
		/* LED D6 */
		gpio6 {
			label = "ls1043s:green:user2";
			gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
		};

		/* SFP+ LEDs - these are for chassis
		 * with lightpipes only
		 */
		teng_act {
			label = "ls1043s:yellow:10gact";
			gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
		};

		teng_link {
			label = "ls1043s:green:10glink";
			gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
		};
	};

	keys {
		compatible = "gpio-keys-polled";
		#address-cells = <1>;
		#size-cells = <0>;
		poll-interval = <1000>;
		/* This button may not be loaded on all boards */
		button@0 {
			label = "Front button";
			linux,code = <KEY_SETUP>;
			gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
		};
		/* This is wired to header S3 */
		button@1 {
			label = "Rear button";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
		};
	};
};

&esdhc {
	mmc-hs200-1_8v;
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
};

&i2c0 {
	status = "okay";
	rtc@6f {
		compatible = "intersil,isl1208";
		reg = <0x6f>;
	};

	sfp_pca9534: pca9534@24 {
		compatible = "ti,tca9534", "nxp,pca9534";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x24>;
		gpio-base = <100>;
	};

	controller@50 {
		compatible = "traverse,controller";
		reg = <0x50>;
	};

	ds125df111@18 {
		compatible = "ti,ds125df111";
		reg = <0x18>;
	};

	emc1704@4c {
		compatible = "microchip,emc1704";
		reg = <0x4c>;
	};

	pac1934@16 {
		compatible = "microchip,pac1934";
		reg = <0x16>;
		/* Monitoring 3.3V, 5V, Vin/12V (voltage only), Vbat/RTC (voltage only) */
		shunt-resistors = <4000 12000 0 0>;
	};

	pmic@8 {
		compatible = "freescale,mc34vr500";
		reg = <0x08>;
	};
};

/* I2C Bus for SFP EEPROM and control
 * These are multiplexed so
 * they don't collide when loaded
 */
&i2c3 {
	status = "okay";
	i2c-switch@70 {
		compatible = "nxp,pca9540";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		gigsfp_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};
		tensfp_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
	};
};

&ifc {
	status = "okay";
	#address-cells = <2>;
	#size-cells = <1>;
	/* Only NAND flash is used on this board */
	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;

	nand@1,0 {
		compatible = "fsl,ifc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0 0x0 0x10000>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

#include "fsl-ls1043-post.dtsi"

&fman0 {
	EMAC0: ethernet@e0000 {
		phy-handle = <&qsgmii_phy1>;
		phy-connection-type = "qsgmii";
		local-mac-address = [0A 00 00 00 00 01];
	};

	EMAC1: ethernet@e2000 {
		phy-handle = <&qsgmii_phy2>;
		phy-connection-type = "qsgmii";
		local-mac-address = [0A 00 00 00 00 02];
	};

	EMAC2: ethernet@e8000 {
		phy-handle = <&qsgmii_phy3>;
		phy-connection-type = "qsgmii";
		local-mac-address = [0A 00 00 00 00 03];
	};

	EMAC3: ethernet@ea000 {
		phy-handle = <&qsgmii_phy4>;
		phy-connection-type = "qsgmii";
		local-mac-address = [0A 00 00 00 00 04];
	};

	/* SFP via AR8031
	 * We treat this as a fixed-link as the
	 * AR8031 is hard-configured into
	 * 1000BASE-X mode
	 * Should MII control be desired, remove
	 * fixed-link and add
	 * phy-handle = <&rgmii_phy1>;
	 */
	EMAC4: ethernet@e4000 {
		phy-connection-type = "rgmii";
		local-mac-address = [0A 00 00 00 00 05];
		fixed-link {
			speed = <1000>;
			full-duplex;
		};
	};

	/* Connection to Expansion (M.2) slot
	 * Future WAN (i.e xDSL) plugin
	 */
	EMAC5: ethernet@e6000 {
		phy-connection-type = "rgmii-id";
		local-mac-address = [00 00 00 00 00 06];
		fixed-link {
			speed = <1000>;
			full-duplex;
		};
	};

	/* 10G SFP+ interface
	 * This can also run at 1.25 and 2.5G with
	 * the appropriate SerDes protocol setting in RCW
	 */
	TENSFP: ethernet@f0000 {
		status = "okay";
		phy-connection-type = "xgmii";
		fixed-link {
			speed = <10000>;
			full-duplex;
		};
	};

	mdio@fc000 {
		rgmii_phy1: ethernet-phy@2 {
			reg = <0x2>;
		};
		qsgmii_phy1: ethernet-phy@4 {
			reg = <0x4>;
		};
		qsgmii_phy2: ethernet-phy@5 {
			reg = <0x5>;
		};
		qsgmii_phy3: ethernet-phy@6 {
			reg = <0x6>;
		};
		qsgmii_phy4: ethernet-phy@7 {
			reg = <0x7>;
		};
	};
};

/* No QUICC engine functions on this board -
 * pins are used for other functions (GPIO, I2C etc.)
 */
&uqe {
	status = "disabled";
};

/* LS1043S does not use the QorIQ AHCI
 * controller.
 */
&sata {
	status = "disabled";
};