bcm6345.dtsi 1.7 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm6345";
  5. aliases {
  6. pflash = &pflash;
  7. serial0 = &uart0;
  8. gpio0 = &gpio0;
  9. };
  10. cpus {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. cpu@0 {
  14. compatible = "brcm,bmips32", "mips,mips4Kc";
  15. device_type = "cpu";
  16. reg = <0>;
  17. };
  18. };
  19. cpu_intc: interrupt-controller {
  20. #address-cells = <0>;
  21. compatible = "mti,cpu-interrupt-controller";
  22. interrupt-controller;
  23. #interrupt-cells = <1>;
  24. };
  25. memory { device_type = "memory"; reg = <0 0>; };
  26. pflash: nor@1fc00000 {
  27. compatible = "cfi-flash";
  28. reg = <0x1fc00000 0x400000>;
  29. bank-width = <2>;
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. status = "disabled";
  33. };
  34. ubus@fff00000 {
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. ranges;
  38. compatible = "simple-bus";
  39. periph_intc: interrupt-controller@fffe000c {
  40. compatible = "brcm,bcm6345-l1-intc";
  41. reg = <0xfffe000c 0x9>;
  42. interrupt-controller;
  43. #interrupt-cells = <1>;
  44. interrupt-parent = <&cpu_intc>;
  45. interrupts = <2>;
  46. };
  47. ext_intc: interrupt-controller@fffe0014 {
  48. compatible = "brcm,bcm6345-ext-intc";
  49. reg = <0xfffe0014 0x4>;
  50. interrupt-controller;
  51. #interrupt-cells = <2>;
  52. interrupt-parent = <&cpu_intc>;
  53. interrupts = <3>, <4>, <5>, <6>;
  54. };
  55. uart0: serial@fffe0300 {
  56. compatible = "brcm,bcm6345-uart";
  57. reg = <0xfffe0300 0x18>;
  58. interrupt-parent = <&periph_intc>;
  59. interrupts = <2>;
  60. /* clocks = <&periph_clk>; */
  61. /* clock-names = "refclk"; */
  62. status = "disabled";
  63. };
  64. gpio0: gpio-controller@fffe0404 {
  65. compatible = "brcm,bcm6345-gpio";
  66. reg = <0xfffe0404 4>, <0xfffe0408 4>;
  67. gpio-controller;
  68. #gpio-cells = <2>;
  69. ngpios = <16>;
  70. };
  71. };
  72. };