0035-v6.3-arm64-dts-qcom-ipq6018-Add-remove-some-newlines.patch 2.9 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192
  1. From 6db9ed9a128cbae1423d043f3debd8bfa77783fd Mon Sep 17 00:00:00 2001
  2. From: Konrad Dybcio <[email protected]>
  3. Date: Mon, 2 Jan 2023 10:46:29 +0100
  4. Subject: [PATCH] arm64: dts: qcom: ipq6018: Add/remove some newlines
  5. Some lines were broken very aggresively, presumably to fit under 80 chars
  6. and some places could have used a newline, particularly between subsequent
  7. nodes. Address all that and remove redundant comments near PCIe ranges
  8. while at it so as not to exceed 100 chars needlessly.
  9. Signed-off-by: Konrad Dybcio <[email protected]>
  10. Signed-off-by: Bjorn Andersson <[email protected]>
  11. Link: https://lore.kernel.org/r/[email protected]
  12. ---
  13. arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++--------------
  14. 1 file changed, 12 insertions(+), 14 deletions(-)
  15. --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  16. +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  17. @@ -102,26 +102,31 @@
  18. opp-microvolt = <725000>;
  19. clock-latency-ns = <200000>;
  20. };
  21. +
  22. opp-1056000000 {
  23. opp-hz = /bits/ 64 <1056000000>;
  24. opp-microvolt = <787500>;
  25. clock-latency-ns = <200000>;
  26. };
  27. +
  28. opp-1320000000 {
  29. opp-hz = /bits/ 64 <1320000000>;
  30. opp-microvolt = <862500>;
  31. clock-latency-ns = <200000>;
  32. };
  33. +
  34. opp-1440000000 {
  35. opp-hz = /bits/ 64 <1440000000>;
  36. opp-microvolt = <925000>;
  37. clock-latency-ns = <200000>;
  38. };
  39. +
  40. opp-1608000000 {
  41. opp-hz = /bits/ 64 <1608000000>;
  42. opp-microvolt = <987500>;
  43. clock-latency-ns = <200000>;
  44. };
  45. +
  46. opp-1800000000 {
  47. opp-hz = /bits/ 64 <1800000000>;
  48. opp-microvolt = <1062500>;
  49. @@ -131,8 +136,7 @@
  50. pmuv8: pmu {
  51. compatible = "arm,cortex-a53-pmu";
  52. - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
  53. - IRQ_TYPE_LEVEL_HIGH)>;
  54. + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  55. };
  56. psci: psci {
  57. @@ -734,24 +738,18 @@
  58. phys = <&pcie_phy0>;
  59. phy-names = "pciephy";
  60. - ranges = <0x81000000 0 0x20200000 0 0x20200000
  61. - 0 0x10000>, /* downstream I/O */
  62. - <0x82000000 0 0x20220000 0 0x20220000
  63. - 0 0xfde0000>; /* non-prefetchable memory */
  64. + ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
  65. + <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
  66. interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  67. interrupt-names = "msi";
  68. #interrupt-cells = <1>;
  69. interrupt-map-mask = <0 0 0 0x7>;
  70. - interrupt-map = <0 0 0 1 &intc 0 75
  71. - IRQ_TYPE_LEVEL_HIGH>, /* int_a */
  72. - <0 0 0 2 &intc 0 78
  73. - IRQ_TYPE_LEVEL_HIGH>, /* int_b */
  74. - <0 0 0 3 &intc 0 79
  75. - IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  76. - <0 0 0 4 &intc 0 83
  77. - IRQ_TYPE_LEVEL_HIGH>; /* int_d */
  78. + interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
  79. + <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
  80. + <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  81. + <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
  82. clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
  83. <&gcc GCC_PCIE0_AXI_M_CLK>,