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- From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001
- From: Krishna Kurapati <[email protected]>
- Date: Fri, 26 Jan 2024 00:29:18 +0530
- Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
- On several QUSB2 Targets, the hs_phy_irq mentioned is actually
- qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
- to qusb2_phy for such targets.
- In actuality, the hs_phy_irq is also present in these targets, but
- kept in for debug purposes in hw test environments. This is not
- triggered by default and its functionality is mutually exclusive
- to that of qusb2_phy interrupt.
- Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
- Add missing ss_phy_irq on some targets which allows for remote
- wakeup to work on a Super Speed link.
- Also modify order of interrupts in accordance to bindings update.
- Since driver looks up for interrupts by name and not by index, it
- is safe to modify order of these interrupts in the DT.
- Signed-off-by: Krishna Kurapati <[email protected]>
- Link: https://lore.kernel.org/r/[email protected]
- Signed-off-by: Bjorn Andersson <[email protected]>
- ---
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
- arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++--
- arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++++--
- arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++--
- arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 +++++++++++++----
- arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++--
- arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++--
- 8 files changed, 70 insertions(+), 14 deletions(-)
- --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
- +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
- @@ -430,6 +430,12 @@
- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
- assigned-clock-rates = <133330000>,
- <24000000>;
- +
- + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- + interrupt-names = "pwr_event",
- + "qusb2_phy";
- +
- resets = <&gcc GCC_USB1_BCR>;
- status = "disabled";
-
- @@ -628,6 +634,13 @@
- <133330000>,
- <24000000>;
-
- + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
- + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
- + interrupt-names = "pwr_event",
- + "qusb2_phy",
- + "ss_phy_irq";
- +
- resets = <&gcc GCC_USB0_BCR>;
- status = "disabled";
-
- --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
- +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
- @@ -611,6 +611,13 @@
- <133330000>,
- <19200000>;
-
- + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
- + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
- + interrupt-names = "pwr_event",
- + "qusb2_phy",
- + "ss_phy_irq";
- +
- power-domains = <&gcc USB0_GDSC>;
-
- resets = <&gcc GCC_USB0_BCR>;
- @@ -653,6 +660,13 @@
- <133330000>,
- <19200000>;
-
- + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- + <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- + interrupt-names = "pwr_event",
- + "qusb2_phy",
- + "ss_phy_irq";
- +
- power-domains = <&gcc USB1_GDSC>;
-
- resets = <&gcc GCC_USB1_BCR>;
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