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0034-v6.3-arm64-dts-qcom-ipq6018-Sort-nodes-properly.patch

0034-v6.3-arm64-dts-qcom-ipq6018-Sort-nodes-properly.patch 16 KB
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  1. From 2c6e322a41c5e1ca45be50b9d5fbcda62dc23a0d Mon Sep 17 00:00:00 2001
    2. 

  2. From: Konrad Dybcio <[email protected]>
    3. 

  3. Date: Mon, 2 Jan 2023 10:46:28 +0100
    4. 

  4. Subject: [PATCH] arm64: dts: qcom: ipq6018: Sort nodes properly
    5. 

  5. 

  6. Order nodes by unit address if one exists and alphabetically otherwise.
    7. 

  7. 

  8. Signed-off-by: Konrad Dybcio <[email protected]>
    9. 

  9. Signed-off-by: Bjorn Andersson <[email protected]>
    10. 

  10. Link: https://lore.kernel.org/r/[email protected]
    11. 

  11. ---
    12. 

  12.  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 562 +++++++++++++-------------
    13. 

  13.  1 file changed, 281 insertions(+), 281 deletions(-)
    14. 

  14. 

  15. --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
    16. 

  16. +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
    17. 

  17. @@ -87,6 +87,12 @@
    18. 

  18.  		};
    19. 

  19.  	};
    20. 

  20.  
    21. 

  21. +	firmware {
    22. 

  22. +		scm {
    23. 

  23. +			compatible = "qcom,scm-ipq6018", "qcom,scm";
    24. 

  24. +		};
    25. 

  25. +	};
    26. 

  26. +
    27. 

  27.  	cpu_opp_table: opp-table-cpu {
    28. 

  28.  		compatible = "operating-points-v2";
    29. 

  29.  		opp-shared;
    30. 

  30. @@ -123,12 +129,6 @@
    31. 

  31.  		};
    32. 

  32.  	};
    33. 

  33.  
    34. 

  34. -	firmware {
    35. 

  35. -		scm {
    36. 

  36. -			compatible = "qcom,scm-ipq6018", "qcom,scm";
    37. 

  37. -		};
    38. 

  38. -	};
    39. 

  39. -
    40. 

  40.  	pmuv8: pmu {
    41. 

  41.  		compatible = "arm,cortex-a53-pmu";
    42. 

  42.  		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
    43. 

  43. @@ -166,6 +166,28 @@
    44. 

  44.  		};
    45. 

  45.  	};
    46. 

  46.  
    47. 

  47. +	rpm-glink {
    48. 

  48. +		compatible = "qcom,glink-rpm";
    49. 

  49. +		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
    50. 

  50. +		qcom,rpm-msg-ram = <&rpm_msg_ram>;
    51. 

  51. +		mboxes = <&apcs_glb 0>;
    52. 

  52. +
    53. 

  53. +		rpm_requests: glink-channel {
    54. 

  54. +			compatible = "qcom,rpm-ipq6018";
    55. 

  55. +			qcom,glink-channels = "rpm_requests";
    56. 

  56. +
    57. 

  57. +			regulators {
    58. 

  58. +				compatible = "qcom,rpm-mp5496-regulators";
    59. 

  59. +
    60. 

  60. +				ipq6018_s2: s2 {
    61. 

  61. +					regulator-min-microvolt = <725000>;
    62. 

  62. +					regulator-max-microvolt = <1062500>;
    63. 

  63. +					regulator-always-on;
    64. 

  64. +				};
    65. 

  65. +			};
    66. 

  66. +		};
    67. 

  67. +	};
    68. 

  68. +
    69. 

  69.  	smem {
    70. 

  70.  		compatible = "qcom,smem";
    71. 

  71.  		memory-region = <&smem_region>;
    72. 

  72. @@ -179,6 +201,102 @@
    73. 

  73.  		dma-ranges;
    74. 

  74.  		compatible = "simple-bus";
    75. 

  75.  
    76. 

  76. +		qusb_phy_1: qusb@59000 {
    77. 

  77. +			compatible = "qcom,ipq6018-qusb2-phy";
    78. 

  78. +			reg = <0x0 0x00059000 0x0 0x180>;
    79. 

  79. +			#phy-cells = <0>;
    80. 

  80. +
    81. 

  81. +			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
    82. 

  82. +				 <&xo>;
    83. 

  83. +			clock-names = "cfg_ahb", "ref";
    84. 

  84. +
    85. 

  85. +			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
    86. 

  86. +			status = "disabled";
    87. 

  87. +		};
    88. 

  88. +
    89. 

  89. +		ssphy_0: ssphy@78000 {
    90. 

  90. +			compatible = "qcom,ipq6018-qmp-usb3-phy";
    91. 

  91. +			reg = <0x0 0x00078000 0x0 0x1c4>;
    92. 

  92. +			#address-cells = <2>;
    93. 

  93. +			#size-cells = <2>;
    94. 

  94. +			ranges;
    95. 

  95. +
    96. 

  96. +			clocks = <&gcc GCC_USB0_AUX_CLK>,
    97. 

  97. +				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
    98. 

  98. +			clock-names = "aux", "cfg_ahb", "ref";
    99. 

  99. +
    100. 

  100. +			resets = <&gcc GCC_USB0_PHY_BCR>,
    101. 

  101. +				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
    102. 

  102. +			reset-names = "phy","common";
    103. 

  103. +			status = "disabled";
    104. 

  104. +
    105. 

  105. +			usb0_ssphy: phy@78200 {
    106. 

  106. +				reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
    107. 

  107. +				      <0x0 0x00078400 0x0 0x200>, /* Rx */
    108. 

  108. +				      <0x0 0x00078800 0x0 0x1f8>, /* PCS */
    109. 

  109. +				      <0x0 0x00078600 0x0 0x044>; /* PCS misc */
    110. 

  110. +				#phy-cells = <0>;
    111. 

  111. +				#clock-cells = <0>;
    112. 

  112. +				clocks = <&gcc GCC_USB0_PIPE_CLK>;
    113. 

  113. +				clock-names = "pipe0";
    114. 

  114. +				clock-output-names = "gcc_usb0_pipe_clk_src";
    115. 

  115. +			};
    116. 

  116. +		};
    117. 

  117. +
    118. 

  118. +		qusb_phy_0: qusb@79000 {
    119. 

  119. +			compatible = "qcom,ipq6018-qusb2-phy";
    120. 

  120. +			reg = <0x0 0x00079000 0x0 0x180>;
    121. 

  121. +			#phy-cells = <0>;
    122. 

  122. +
    123. 

  123. +			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
    124. 

  124. +				<&xo>;
    125. 

  125. +			clock-names = "cfg_ahb", "ref";
    126. 

  126. +
    127. 

  127. +			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
    128. 

  128. +			status = "disabled";
    129. 

  129. +		};
    130. 

  130. +
    131. 

  131. +		pcie_phy: phy@84000 {
    132. 

  132. +			compatible = "qcom,ipq6018-qmp-pcie-phy";
    133. 

  133. +			reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
    134. 

  134. +			status = "disabled";
    135. 

  135. +			#address-cells = <2>;
    136. 

  136. +			#size-cells = <2>;
    137. 

  137. +			ranges;
    138. 

  138. +
    139. 

  139. +			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
    140. 

  140. +				<&gcc GCC_PCIE0_AHB_CLK>;
    141. 

  141. +			clock-names = "aux", "cfg_ahb";
    142. 

  142. +
    143. 

  143. +			resets = <&gcc GCC_PCIE0_PHY_BCR>,
    144. 

  144. +				<&gcc GCC_PCIE0PHY_PHY_BCR>;
    145. 

  145. +			reset-names = "phy",
    146. 

  146. +				      "common";
    147. 

  147. +
    148. 

  148. +			pcie_phy0: phy@84200 {
    149. 

  149. +				reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
    150. 

  150. +				      <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
    151. 

  151. +				      <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
    152. 

  152. +				      <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
    153. 

  153. +				#phy-cells = <0>;
    154. 

  154. +
    155. 

  155. +				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
    156. 

  156. +				clock-names = "pipe0";
    157. 

  157. +				clock-output-names = "gcc_pcie0_pipe_clk_src";
    158. 

  158. +				#clock-cells = <0>;
    159. 

  159. +			};
    160. 

  160. +		};
    161. 

  161. +
    162. 

  162. +		mdio: mdio@90000 {
    163. 

  163. +			#address-cells = <1>;
    164. 

  164. +			#size-cells = <0>;
    165. 

  165. +			compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
    166. 

  166. +			reg = <0x0 0x00090000 0x0 0x64>;
    167. 

  167. +			clocks = <&gcc GCC_MDIO_AHB_CLK>;
    168. 

  168. +			clock-names = "gcc_mdio_ahb_clk";
    169. 

  169. +			status = "disabled";
    170. 

  170. +		};
    171. 

  171. +
    172. 

  172.  		prng: qrng@e1000 {
    173. 

  173.  			compatible = "qcom,prng-ee";
    174. 

  174.  			reg = <0x0 0x000e3000 0x0 0x1000>;
    175. 

  175. @@ -257,6 +375,41 @@
    176. 

  176.  			reg = <0x0 0x01937000 0x0 0x21000>;
    177. 

  177.  		};
    178. 

  178.  
    179. 

  179. +		usb2: usb@70f8800 {
    180. 

  180. +			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
    181. 

  181. +			reg = <0x0 0x070F8800 0x0 0x400>;
    182. 

  182. +			#address-cells = <2>;
    183. 

  183. +			#size-cells = <2>;
    184. 

  184. +			ranges;
    185. 

  185. +			clocks = <&gcc GCC_USB1_MASTER_CLK>,
    186. 

  186. +				 <&gcc GCC_USB1_SLEEP_CLK>,
    187. 

  187. +				 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
    188. 

  188. +			clock-names = "core",
    189. 

  189. +				      "sleep",
    190. 

  190. +				      "mock_utmi";
    191. 

  191. +
    192. 

  192. +			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
    193. 

  193. +					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
    194. 

  194. +			assigned-clock-rates = <133330000>,
    195. 

  195. +					       <24000000>;
    196. 

  196. +			resets = <&gcc GCC_USB1_BCR>;
    197. 

  197. +			status = "disabled";
    198. 

  198. +
    199. 

  199. +			dwc_1: usb@7000000 {
    200. 

  200. +				compatible = "snps,dwc3";
    201. 

  201. +				reg = <0x0 0x07000000 0x0 0xcd00>;
    202. 

  202. +				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
    203. 

  203. +				phys = <&qusb_phy_1>;
    204. 

  204. +				phy-names = "usb2-phy";
    205. 

  205. +				tx-fifo-resize;
    206. 

  206. +				snps,is-utmi-l1-suspend;
    207. 

  207. +				snps,hird-threshold = /bits/ 8 <0x0>;
    208. 

  208. +				snps,dis_u2_susphy_quirk;
    209. 

  209. +				snps,dis_u3_susphy_quirk;
    210. 

  210. +				dr_mode = "host";
    211. 

  211. +			};
    212. 

  212. +		};
    213. 

  213. +
    214. 

  214.  		blsp_dma: dma-controller@7884000 {
    215. 

  215.  			compatible = "qcom,bam-v1.7.0";
    216. 

  216.  			reg = <0x0 0x07884000 0x0 0x2b000>;
    217. 

  217. @@ -366,6 +519,49 @@
    218. 

  218.  			status = "disabled";
    219. 

  219.  		};
    220. 

  220.  
    221. 

  221. +		usb3: usb@8af8800 {
    222. 

  222. +			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
    223. 

  223. +			reg = <0x0 0x08af8800 0x0 0x400>;
    224. 

  224. +			#address-cells = <2>;
    225. 

  225. +			#size-cells = <2>;
    226. 

  226. +			ranges;
    227. 

  227. +
    228. 

  228. +			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
    229. 

  229. +				<&gcc GCC_USB0_MASTER_CLK>,
    230. 

  230. +				<&gcc GCC_USB0_SLEEP_CLK>,
    231. 

  231. +				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
    232. 

  232. +			clock-names = "cfg_noc",
    233. 

  233. +				"core",
    234. 

  234. +				"sleep",
    235. 

  235. +				"mock_utmi";
    236. 

  236. +
    237. 

  237. +			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
    238. 

  238. +					  <&gcc GCC_USB0_MASTER_CLK>,
    239. 

  239. +					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
    240. 

  240. +			assigned-clock-rates = <133330000>,
    241. 

  241. +					       <133330000>,
    242. 

  242. +					       <24000000>;
    243. 

  243. +
    244. 

  244. +			resets = <&gcc GCC_USB0_BCR>;
    245. 

  245. +			status = "disabled";
    246. 

  246. +
    247. 

  247. +			dwc_0: usb@8a00000 {
    248. 

  248. +				compatible = "snps,dwc3";
    249. 

  249. +				reg = <0x0 0x08a00000 0x0 0xcd00>;
    250. 

  250. +				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
    251. 

  251. +				phys = <&qusb_phy_0>, <&usb0_ssphy>;
    252. 

  252. +				phy-names = "usb2-phy", "usb3-phy";
    253. 

  253. +				clocks = <&xo>;
    254. 

  254. +				clock-names = "ref";
    255. 

  255. +				tx-fifo-resize;
    256. 

  256. +				snps,is-utmi-l1-suspend;
    257. 

  257. +				snps,hird-threshold = /bits/ 8 <0x0>;
    258. 

  258. +				snps,dis_u2_susphy_quirk;
    259. 

  259. +				snps,dis_u3_susphy_quirk;
    260. 

  260. +				dr_mode = "host";
    261. 

  261. +			};
    262. 

  262. +		};
    263. 

  263. +
    264. 

  264.  		intc: interrupt-controller@b000000 {
    265. 

  265.  			compatible = "qcom,msm-qgic2";
    266. 

  266.  			#address-cells = <2>;
    267. 

  267. @@ -386,105 +582,6 @@
    268. 

  268.  			};
    269. 

  269.  		};
    270. 

  270.  
    271. 

  271. -		pcie_phy: phy@84000 {
    272. 

  272. -			compatible = "qcom,ipq6018-qmp-pcie-phy";
    273. 

  273. -			reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
    274. 

  274. -			status = "disabled";
    275. 

  275. -			#address-cells = <2>;
    276. 

  276. -			#size-cells = <2>;
    277. 

  277. -			ranges;
    278. 

  278. -
    279. 

  279. -			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
    280. 

  280. -				<&gcc GCC_PCIE0_AHB_CLK>;
    281. 

  281. -			clock-names = "aux", "cfg_ahb";
    282. 

  282. -
    283. 

  283. -			resets = <&gcc GCC_PCIE0_PHY_BCR>,
    284. 

  284. -				<&gcc GCC_PCIE0PHY_PHY_BCR>;
    285. 

  285. -			reset-names = "phy",
    286. 

  286. -				      "common";
    287. 

  287. -
    288. 

  288. -			pcie_phy0: phy@84200 {
    289. 

  289. -				reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
    290. 

  290. -				      <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
    291. 

  291. -				      <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
    292. 

  292. -				      <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
    293. 

  293. -				#phy-cells = <0>;
    294. 

  294. -
    295. 

  295. -				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
    296. 

  296. -				clock-names = "pipe0";
    297. 

  297. -				clock-output-names = "gcc_pcie0_pipe_clk_src";
    298. 

  298. -				#clock-cells = <0>;
    299. 

  299. -			};
    300. 

  300. -		};
    301. 

  301. -
    302. 

  302. -		pcie0: pci@20000000 {
    303. 

  303. -			compatible = "qcom,pcie-ipq6018";
    304. 

  304. -			reg = <0x0 0x20000000 0x0 0xf1d>,
    305. 

  305. -			      <0x0 0x20000f20 0x0 0xa8>,
    306. 

  306. -			      <0x0 0x20001000 0x0 0x1000>,
    307. 

  307. -			      <0x0 0x80000 0x0 0x4000>,
    308. 

  308. -			      <0x0 0x20100000 0x0 0x1000>;
    309. 

  309. -			reg-names = "dbi", "elbi", "atu", "parf", "config";
    310. 

  310. -
    311. 

  311. -			device_type = "pci";
    312. 

  312. -			linux,pci-domain = <0>;
    313. 

  313. -			bus-range = <0x00 0xff>;
    314. 

  314. -			num-lanes = <1>;
    315. 

  315. -			max-link-speed = <3>;
    316. 

  316. -			#address-cells = <3>;
    317. 

  317. -			#size-cells = <2>;
    318. 

  318. -
    319. 

  319. -			phys = <&pcie_phy0>;
    320. 

  320. -			phy-names = "pciephy";
    321. 

  321. -
    322. 

  322. -			ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
    323. 

  323. -				 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
    324. 

  324. -
    325. 

  325. -			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
    326. 

  326. -			interrupt-names = "msi";
    327. 

  327. -
    328. 

  328. -			#interrupt-cells = <1>;
    329. 

  329. -			interrupt-map-mask = <0 0 0 0x7>;
    330. 

  330. -			interrupt-map = <0 0 0 1 &intc 0 75
    331. 

  331. -					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
    332. 

  332. -					<0 0 0 2 &intc 0 78
    333. 

  333. -					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
    334. 

  334. -					<0 0 0 3 &intc 0 79
    335. 

  335. -					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
    336. 

  336. -					<0 0 0 4 &intc 0 83
    337. 

  337. -					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
    338. 

  338. -
    339. 

  339. -			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
    340. 

  340. -				 <&gcc GCC_PCIE0_AXI_M_CLK>,
    341. 

  341. -				 <&gcc GCC_PCIE0_AXI_S_CLK>,
    342. 

  342. -				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
    343. 

  343. -				 <&gcc PCIE0_RCHNG_CLK>;
    344. 

  344. -			clock-names = "iface",
    345. 

  345. -				      "axi_m",
    346. 

  346. -				      "axi_s",
    347. 

  347. -				      "axi_bridge",
    348. 

  348. -				      "rchng";
    349. 

  349. -
    350. 

  350. -			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
    351. 

  351. -				 <&gcc GCC_PCIE0_SLEEP_ARES>,
    352. 

  352. -				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
    353. 

  353. -				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
    354. 

  354. -				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
    355. 

  355. -				 <&gcc GCC_PCIE0_AHB_ARES>,
    356. 

  356. -				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
    357. 

  357. -				 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
    358. 

  358. -			reset-names = "pipe",
    359. 

  359. -				      "sleep",
    360. 

  360. -				      "sticky",
    361. 

  361. -				      "axi_m",
    362. 

  362. -				      "axi_s",
    363. 

  363. -				      "ahb",
    364. 

  364. -				      "axi_m_sticky",
    365. 

  365. -				      "axi_s_sticky";
    366. 

  366. -
    367. 

  367. -			status = "disabled";
    368. 

  368. -		};
    369. 

  369. -
    370. 

  370.  		watchdog@b017000 {
    371. 

  371.  			compatible = "qcom,kpss-wdt";
    372. 

  372.  			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
    373. 

  373. @@ -617,147 +714,74 @@
    374. 

  374.  			};
    375. 

  375.  		};
    376. 

  376.  
    377. 

  377. -		mdio: mdio@90000 {
    378. 

  378. -			#address-cells = <1>;
    379. 

  379. -			#size-cells = <0>;
    380. 

  380. -			compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
    381. 

  381. -			reg = <0x0 0x00090000 0x0 0x64>;
    382. 

  382. -			clocks = <&gcc GCC_MDIO_AHB_CLK>;
    383. 

  383. -			clock-names = "gcc_mdio_ahb_clk";
    384. 

  384. -			status = "disabled";
    385. 

  385. -		};
    386. 

  386. -
    387. 

  387. -		qusb_phy_1: qusb@59000 {
    388. 

  388. -			compatible = "qcom,ipq6018-qusb2-phy";
    389. 

  389. -			reg = <0x0 0x00059000 0x0 0x180>;
    390. 

  390. -			#phy-cells = <0>;
    391. 

  391. -
    392. 

  392. -			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
    393. 

  393. -				 <&xo>;
    394. 

  394. -			clock-names = "cfg_ahb", "ref";
    395. 

  395. -
    396. 

  396. -			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
    397. 

  397. -			status = "disabled";
    398. 

  398. -		};
    399. 

  399. -
    400. 

  400. -		usb2: usb@70f8800 {
    401. 

  401. -			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
    402. 

  402. -			reg = <0x0 0x070F8800 0x0 0x400>;
    403. 

  403. -			#address-cells = <2>;
    404. 

  404. -			#size-cells = <2>;
    405. 

  405. -			ranges;
    406. 

  406. -			clocks = <&gcc GCC_USB1_MASTER_CLK>,
    407. 

  407. -				 <&gcc GCC_USB1_SLEEP_CLK>,
    408. 

  408. -				 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
    409. 

  409. -			clock-names = "core",
    410. 

  410. -				      "sleep",
    411. 

  411. -				      "mock_utmi";
    412. 

  412. -
    413. 

  413. -			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
    414. 

  414. -					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
    415. 

  415. -			assigned-clock-rates = <133330000>,
    416. 

  416. -					       <24000000>;
    417. 

  417. -			resets = <&gcc GCC_USB1_BCR>;
    418. 

  418. -			status = "disabled";
    419. 

  419. -
    420. 

  420. -			dwc_1: usb@7000000 {
    421. 

  421. -				compatible = "snps,dwc3";
    422. 

  422. -				reg = <0x0 0x07000000 0x0 0xcd00>;
    423. 

  423. -				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
    424. 

  424. -				phys = <&qusb_phy_1>;
    425. 

  425. -				phy-names = "usb2-phy";
    426. 

  426. -				tx-fifo-resize;
    427. 

  427. -				snps,is-utmi-l1-suspend;
    428. 

  428. -				snps,hird-threshold = /bits/ 8 <0x0>;
    429. 

  429. -				snps,dis_u2_susphy_quirk;
    430. 

  430. -				snps,dis_u3_susphy_quirk;
    431. 

  431. -				dr_mode = "host";
    432. 

  432. -			};
    433. 

  433. -		};
    434. 

  434. +		pcie0: pci@20000000 {
    435. 

  435. +			compatible = "qcom,pcie-ipq6018";
    436. 

  436. +			reg = <0x0 0x20000000 0x0 0xf1d>,
    437. 

  437. +			      <0x0 0x20000f20 0x0 0xa8>,
    438. 

  438. +			      <0x0 0x20001000 0x0 0x1000>,
    439. 

  439. +			      <0x0 0x80000 0x0 0x4000>,
    440. 

  440. +			      <0x0 0x20100000 0x0 0x1000>;
    441. 

  441. +			reg-names = "dbi", "elbi", "atu", "parf", "config";
    442. 

  442.  
    443. 

  443. -		ssphy_0: ssphy@78000 {
    444. 

  444. -			compatible = "qcom,ipq6018-qmp-usb3-phy";
    445. 

  445. -			reg = <0x0 0x00078000 0x0 0x1c4>;
    446. 

  446. -			#address-cells = <2>;
    447. 

  447. +			device_type = "pci";
    448. 

  448. +			linux,pci-domain = <0>;
    449. 

  449. +			bus-range = <0x00 0xff>;
    450. 

  450. +			num-lanes = <1>;
    451. 

  451. +			max-link-speed = <3>;
    452. 

  452. +			#address-cells = <3>;
    453. 

  453.  			#size-cells = <2>;
    454. 

  454. -			ranges;
    455. 

  455. -
    456. 

  456. -			clocks = <&gcc GCC_USB0_AUX_CLK>,
    457. 

  457. -				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
    458. 

  458. -			clock-names = "aux", "cfg_ahb", "ref";
    459. 

  459. -
    460. 

  460. -			resets = <&gcc GCC_USB0_PHY_BCR>,
    461. 

  461. -				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
    462. 

  462. -			reset-names = "phy","common";
    463. 

  463. -			status = "disabled";
    464. 

  464. -
    465. 

  465. -			usb0_ssphy: phy@78200 {
    466. 

  466. -				reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
    467. 

  467. -				      <0x0 0x00078400 0x0 0x200>, /* Rx */
    468. 

  468. -				      <0x0 0x00078800 0x0 0x1f8>, /* PCS */
    469. 

  469. -				      <0x0 0x00078600 0x0 0x044>; /* PCS misc */
    470. 

  470. -				#phy-cells = <0>;
    471. 

  471. -				#clock-cells = <0>;
    472. 

  472. -				clocks = <&gcc GCC_USB0_PIPE_CLK>;
    473. 

  473. -				clock-names = "pipe0";
    474. 

  474. -				clock-output-names = "gcc_usb0_pipe_clk_src";
    475. 

  475. -			};
    476. 

  476. -		};
    477. 

  477.  
    478. 

  478. -		qusb_phy_0: qusb@79000 {
    479. 

  479. -			compatible = "qcom,ipq6018-qusb2-phy";
    480. 

  480. -			reg = <0x0 0x00079000 0x0 0x180>;
    481. 

  481. -			#phy-cells = <0>;
    482. 

  482. +			phys = <&pcie_phy0>;
    483. 

  483. +			phy-names = "pciephy";
    484. 

  484.  
    485. 

  485. -			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
    486. 

  486. -				<&xo>;
    487. 

  487. -			clock-names = "cfg_ahb", "ref";
    488. 

  488. +			ranges = <0x81000000 0 0x20200000 0 0x20200000
    489. 

  489. +				  0 0x10000>, /* downstream I/O */
    490. 

  490. +				 <0x82000000 0 0x20220000 0 0x20220000
    491. 

  491. +				  0 0xfde0000>; /* non-prefetchable memory */
    492. 

  492.  
    493. 

  493. -			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
    494. 

  494. -			status = "disabled";
    495. 

  495. -		};
    496. 

  496. +			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
    497. 

  497. +			interrupt-names = "msi";
    498. 

  498.  
    499. 

  499. -		usb3: usb@8af8800 {
    500. 

  500. -			compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
    501. 

  501. -			reg = <0x0 0x8af8800 0x0 0x400>;
    502. 

  502. -			#address-cells = <2>;
    503. 

  503. -			#size-cells = <2>;
    504. 

  504. -			ranges;
    505. 

  505. +			#interrupt-cells = <1>;
    506. 

  506. +			interrupt-map-mask = <0 0 0 0x7>;
    507. 

  507. +			interrupt-map = <0 0 0 1 &intc 0 75
    508. 

  508. +					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
    509. 

  509. +					<0 0 0 2 &intc 0 78
    510. 

  510. +					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
    511. 

  511. +					<0 0 0 3 &intc 0 79
    512. 

  512. +					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
    513. 

  513. +					<0 0 0 4 &intc 0 83
    514. 

  514. +					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
    515. 

  515.  
    516. 

  516. -			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
    517. 

  517. -				<&gcc GCC_USB0_MASTER_CLK>,
    518. 

  518. -				<&gcc GCC_USB0_SLEEP_CLK>,
    519. 

  519. -				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
    520. 

  520. -			clock-names = "cfg_noc",
    521. 

  521. -				"core",
    522. 

  522. -				"sleep",
    523. 

  523. -				"mock_utmi";
    524. 

  524. +			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
    525. 

  525. +				 <&gcc GCC_PCIE0_AXI_M_CLK>,
    526. 

  526. +				 <&gcc GCC_PCIE0_AXI_S_CLK>,
    527. 

  527. +				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
    528. 

  528. +				 <&gcc PCIE0_RCHNG_CLK>;
    529. 

  529. +			clock-names = "iface",
    530. 

  530. +				      "axi_m",
    531. 

  531. +				      "axi_s",
    532. 

  532. +				      "axi_bridge",
    533. 

  533. +				      "rchng";
    534. 

  534.  
    535. 

  535. -			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
    536. 

  536. -					  <&gcc GCC_USB0_MASTER_CLK>,
    537. 

  537. -					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
    538. 

  538. -			assigned-clock-rates = <133330000>,
    539. 

  539. -					       <133330000>,
    540. 

  540. -					       <24000000>;
    541. 

  541. +			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
    542. 

  542. +				 <&gcc GCC_PCIE0_SLEEP_ARES>,
    543. 

  543. +				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
    544. 

  544. +				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
    545. 

  545. +				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
    546. 

  546. +				 <&gcc GCC_PCIE0_AHB_ARES>,
    547. 

  547. +				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
    548. 

  548. +				 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
    549. 

  549. +			reset-names = "pipe",
    550. 

  550. +				      "sleep",
    551. 

  551. +				      "sticky",
    552. 

  552. +				      "axi_m",
    553. 

  553. +				      "axi_s",
    554. 

  554. +				      "ahb",
    555. 

  555. +				      "axi_m_sticky",
    556. 

  556. +				      "axi_s_sticky";
    557. 

  557.  
    558. 

  558. -			resets = <&gcc GCC_USB0_BCR>;
    559. 

  559.  			status = "disabled";
    560. 

  560. -
    561. 

  561. -			dwc_0: usb@8a00000 {
    562. 

  562. -				compatible = "snps,dwc3";
    563. 

  563. -				reg = <0x0 0x8a00000 0x0 0xcd00>;
    564. 

  564. -				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
    565. 

  565. -				phys = <&qusb_phy_0>, <&usb0_ssphy>;
    566. 

  566. -				phy-names = "usb2-phy", "usb3-phy";
    567. 

  567. -				clocks = <&xo>;
    568. 

  568. -				clock-names = "ref";
    569. 

  569. -				tx-fifo-resize;
    570. 

  570. -				snps,is-utmi-l1-suspend;
    571. 

  571. -				snps,hird-threshold = /bits/ 8 <0x0>;
    572. 

  572. -				snps,dis_u2_susphy_quirk;
    573. 

  573. -				snps,dis_u3_susphy_quirk;
    574. 

  574. -				dr_mode = "host";
    575. 

  575. -			};
    576. 

  576.  		};
    577. 

  577.  	};
    578. 

  578.  
    579. 

  579. @@ -792,26 +816,4 @@
    580. 

  580.  			#interrupt-cells = <2>;
    581. 

  581.  		};
    582. 

  582.  	};
    583. 

  583. -
    584. 

  584. -	rpm-glink {
    585. 

  585. -		compatible = "qcom,glink-rpm";
    586. 

  586. -		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
    587. 

  587. -		qcom,rpm-msg-ram = <&rpm_msg_ram>;
    588. 

  588. -		mboxes = <&apcs_glb 0>;
    589. 

  589. -
    590. 

  590. -		rpm_requests: glink-channel {
    591. 

  591. -			compatible = "qcom,rpm-ipq6018";
    592. 

  592. -			qcom,glink-channels = "rpm_requests";
    593. 

  593. -
    594. 

  594. -			regulators {
    595. 

  595. -				compatible = "qcom,rpm-mp5496-regulators";
    596. 

  596. -
    597. 

  597. -				ipq6018_s2: s2 {
    598. 

  598. -					regulator-min-microvolt = <725000>;
    599. 

  599. -					regulator-max-microvolt = <1062500>;
    600. 

  600. -					regulator-always-on;
    601. 

  601. -				};
    602. 

  602. -			};
    603. 

  603. -		};
    604. 

  604. -	};
    605. 

  605.  };
    606.