312-v4.16-0004-brcmfmac-Rename-replace-old-IO-functions-with-simple.patch 28 KB

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  1. From 71bd508d7ded8c504ef05d1b4befecfe25e54cb1 Mon Sep 17 00:00:00 2001
  2. From: Ian Molton <[email protected]>
  3. Date: Fri, 8 Dec 2017 13:10:29 +0100
  4. Subject: [PATCH] brcmfmac: Rename / replace old IO functions with simpler
  5. ones.
  6. Primarily this patch removes:
  7. brcmf_sdiod_f0_writeb()
  8. brcmf_sdiod_reg_write()
  9. brcmf_sdiod_reg_read()
  10. Since we no longer use the quirky method of deciding which function to
  11. address via the address being accessed, take the opportunity to rename
  12. some IO functions more in line with common kernel code. We also convert
  13. those that map directly to sdio_{read,write}*() to macros.
  14. Signed-off-by: Ian Molton <[email protected]>
  15. Reviewed-by: Arend van Spriel <[email protected]>
  16. Signed-off-by: Arend van Spriel <[email protected]>
  17. Signed-off-by: Kalle Valo <[email protected]>
  18. ---
  19. .../wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c | 169 +++----------------
  20. .../wireless/broadcom/brcm80211/brcmfmac/sdio.c | 186 ++++++++++-----------
  21. .../wireless/broadcom/brcm80211/brcmfmac/sdio.h | 28 +++-
  22. 3 files changed, 138 insertions(+), 245 deletions(-)
  23. --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
  24. +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/bcmsdh.c
  25. @@ -137,27 +137,27 @@ int brcmf_sdiod_intr_register(struct brc
  26. if (sdiodev->bus_if->chip == BRCM_CC_43362_CHIP_ID) {
  27. /* assign GPIO to SDIO core */
  28. addr = CORE_CC_REG(SI_ENUM_BASE, gpiocontrol);
  29. - gpiocontrol = brcmf_sdiod_regrl(sdiodev, addr, &ret);
  30. + gpiocontrol = brcmf_sdiod_readl(sdiodev, addr, &ret);
  31. gpiocontrol |= 0x2;
  32. - brcmf_sdiod_regwl(sdiodev, addr, gpiocontrol, &ret);
  33. + brcmf_sdiod_writel(sdiodev, addr, gpiocontrol, &ret);
  34. - brcmf_sdiod_regwb(sdiodev, SBSDIO_GPIO_SELECT, 0xf,
  35. - &ret);
  36. - brcmf_sdiod_regwb(sdiodev, SBSDIO_GPIO_OUT, 0, &ret);
  37. - brcmf_sdiod_regwb(sdiodev, SBSDIO_GPIO_EN, 0x2, &ret);
  38. + brcmf_sdiod_writeb(sdiodev, SBSDIO_GPIO_SELECT,
  39. + 0xf, &ret);
  40. + brcmf_sdiod_writeb(sdiodev, SBSDIO_GPIO_OUT, 0, &ret);
  41. + brcmf_sdiod_writeb(sdiodev, SBSDIO_GPIO_EN, 0x2, &ret);
  42. }
  43. /* must configure SDIO_CCCR_IENx to enable irq */
  44. - data = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_IENx, &ret);
  45. + data = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_IENx, &ret);
  46. data |= 1 << SDIO_FUNC_1 | 1 << SDIO_FUNC_2 | 1;
  47. - brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_IENx, data, &ret);
  48. + brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_IENx, data, &ret);
  49. /* redirect, configure and enable io for interrupt signal */
  50. data = SDIO_SEPINT_MASK | SDIO_SEPINT_OE;
  51. if (pdata->oob_irq_flags & IRQF_TRIGGER_HIGH)
  52. data |= SDIO_SEPINT_ACT_HI;
  53. - brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_SEPINT, data, &ret);
  54. -
  55. + brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_SEPINT,
  56. + data, &ret);
  57. sdio_release_host(sdiodev->func[1]);
  58. } else {
  59. brcmf_dbg(SDIO, "Entering\n");
  60. @@ -183,8 +183,8 @@ void brcmf_sdiod_intr_unregister(struct
  61. pdata = &sdiodev->settings->bus.sdio;
  62. sdio_claim_host(sdiodev->func[1]);
  63. - brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_SEPINT, 0, NULL);
  64. - brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_IENx, 0, NULL);
  65. + brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_SEPINT, 0, NULL);
  66. + brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_IENx, 0, NULL);
  67. sdio_release_host(sdiodev->func[1]);
  68. sdiodev->oob_irq_requested = false;
  69. @@ -242,8 +242,8 @@ static int brcmf_sdiod_set_sbaddr_window
  70. addr = (address & SBSDIO_SBWINDOW_MASK) >> 8;
  71. for (i = 0 ; i < 3 && !err ; i++, addr >>= 8)
  72. - brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SBADDRLOW + i,
  73. - addr & 0xff, &err);
  74. + brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SBADDRLOW + i,
  75. + addr & 0xff, &err);
  76. return err;
  77. }
  78. @@ -267,124 +267,15 @@ static int brcmf_sdiod_addrprep(struct b
  79. return 0;
  80. }
  81. -static inline int brcmf_sdiod_f0_writeb(struct sdio_func *func, u8 byte,
  82. - uint regaddr)
  83. -{
  84. - int err_ret;
  85. -
  86. - /*
  87. - * Can only directly write to some F0 registers.
  88. - * Handle CCCR_IENx and CCCR_ABORT command
  89. - * as a special case.
  90. - */
  91. - if ((regaddr == SDIO_CCCR_ABORT) ||
  92. - (regaddr == SDIO_CCCR_IENx))
  93. - sdio_writeb(func, byte, regaddr, &err_ret);
  94. - else
  95. - sdio_f0_writeb(func, byte, regaddr, &err_ret);
  96. -
  97. - return err_ret;
  98. -}
  99. -
  100. -static int brcmf_sdiod_reg_write(struct brcmf_sdio_dev *sdiodev, u32 addr,
  101. - u8 regsz, void *data)
  102. -{
  103. - int ret;
  104. -
  105. - /*
  106. - * figure out how to read the register based on address range
  107. - * 0x00 ~ 0x7FF: function 0 CCCR and FBR
  108. - * 0x10000 ~ 0x1FFFF: function 1 miscellaneous registers
  109. - * The rest: function 1 silicon backplane core registers
  110. - * f0 writes must be bytewise
  111. - */
  112. -
  113. - if ((addr & ~REG_F0_REG_MASK) == 0) {
  114. - if (WARN_ON(regsz > 1))
  115. - return -EINVAL;
  116. - ret = brcmf_sdiod_f0_writeb(sdiodev->func[0],
  117. - *(u8 *)data, addr);
  118. - } else {
  119. - switch (regsz) {
  120. - case 1:
  121. - sdio_writeb(sdiodev->func[1], *(u8 *)data, addr, &ret);
  122. - break;
  123. - case 4:
  124. - ret = brcmf_sdiod_addrprep(sdiodev, &addr);
  125. - if (ret)
  126. - goto done;
  127. -
  128. - sdio_writel(sdiodev->func[1], *(u32 *)data, addr, &ret);
  129. - break;
  130. - default:
  131. - WARN(1, "Invalid reg size\n");
  132. - ret = -EINVAL;
  133. - break;
  134. - }
  135. - }
  136. -
  137. -done:
  138. - return ret;
  139. -}
  140. -
  141. -static int brcmf_sdiod_reg_read(struct brcmf_sdio_dev *sdiodev, u32 addr,
  142. - u8 regsz, void *data)
  143. -{
  144. - int ret;
  145. -
  146. - /*
  147. - * figure out how to read the register based on address range
  148. - * 0x00 ~ 0x7FF: function 0 CCCR and FBR
  149. - * 0x10000 ~ 0x1FFFF: function 1 miscellaneous registers
  150. - * The rest: function 1 silicon backplane core registers
  151. - * f0 reads must be bytewise
  152. - */
  153. - if ((addr & ~REG_F0_REG_MASK) == 0) {
  154. - if (WARN_ON(regsz > 1))
  155. - return -EINVAL;
  156. - *(u8 *)data = sdio_f0_readb(sdiodev->func[0], addr, &ret);
  157. - } else {
  158. - switch (regsz) {
  159. - case 1:
  160. - *(u8 *)data = sdio_readb(sdiodev->func[1], addr, &ret);
  161. - break;
  162. - case 4:
  163. - ret = brcmf_sdiod_addrprep(sdiodev, &addr);
  164. - if (ret)
  165. - goto done;
  166. -
  167. - *(u32 *)data = sdio_readl(sdiodev->func[1], addr, &ret);
  168. - break;
  169. - default:
  170. - WARN(1, "Invalid reg size\n");
  171. - ret = -EINVAL;
  172. - break;
  173. - }
  174. - }
  175. -
  176. -done:
  177. - return ret;
  178. -}
  179. -
  180. -u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret)
  181. +u32 brcmf_sdiod_readl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret)
  182. {
  183. - u8 data;
  184. + u32 data = 0;
  185. int retval;
  186. - retval = brcmf_sdiod_reg_read(sdiodev, addr, 1, &data);
  187. -
  188. - if (ret)
  189. - *ret = retval;
  190. -
  191. - return data;
  192. -}
  193. + retval = brcmf_sdiod_addrprep(sdiodev, &addr);
  194. -u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret)
  195. -{
  196. - u32 data;
  197. - int retval;
  198. -
  199. - retval = brcmf_sdiod_reg_read(sdiodev, addr, 4, &data);
  200. + if (!retval)
  201. + data = sdio_readl(sdiodev->func[1], addr, &retval);
  202. if (ret)
  203. *ret = retval;
  204. @@ -392,23 +283,15 @@ u32 brcmf_sdiod_regrl(struct brcmf_sdio_
  205. return data;
  206. }
  207. -void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr,
  208. - u8 data, int *ret)
  209. +void brcmf_sdiod_writel(struct brcmf_sdio_dev *sdiodev, u32 addr,
  210. + u32 data, int *ret)
  211. {
  212. int retval;
  213. - retval = brcmf_sdiod_reg_write(sdiodev, addr, 1, &data);
  214. -
  215. - if (ret)
  216. - *ret = retval;
  217. -}
  218. -
  219. -void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr,
  220. - u32 data, int *ret)
  221. -{
  222. - int retval;
  223. + retval = brcmf_sdiod_addrprep(sdiodev, &addr);
  224. - retval = brcmf_sdiod_reg_write(sdiodev, addr, 4, &data);
  225. + if (!retval)
  226. + sdio_writel(sdiodev->func[1], data, addr, &retval);
  227. if (ret)
  228. *ret = retval;
  229. @@ -846,8 +729,8 @@ int brcmf_sdiod_abort(struct brcmf_sdio_
  230. {
  231. brcmf_dbg(SDIO, "Enter\n");
  232. - /* issue abort cmd52 command through F0 */
  233. - brcmf_sdiod_reg_write(sdiodev, SDIO_CCCR_ABORT, 1, &fn);
  234. + /* Issue abort cmd52 command through F0 */
  235. + brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_ABORT, fn, NULL);
  236. brcmf_dbg(SDIO, "Exit\n");
  237. return 0;
  238. --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
  239. +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
  240. @@ -669,7 +669,7 @@ static int r_sdreg32(struct brcmf_sdio *
  241. int ret;
  242. core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
  243. - *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
  244. + *regvar = brcmf_sdiod_readl(bus->sdiodev, core->base + offset, &ret);
  245. return ret;
  246. }
  247. @@ -680,7 +680,7 @@ static int w_sdreg32(struct brcmf_sdio *
  248. int ret;
  249. core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
  250. - brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
  251. + brcmf_sdiod_writel(bus->sdiodev, core->base + reg_offset, regval, &ret);
  252. return ret;
  253. }
  254. @@ -697,8 +697,7 @@ brcmf_sdio_kso_control(struct brcmf_sdio
  255. wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
  256. /* 1st KSO write goes to AOS wake up core if device is asleep */
  257. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  258. - wr_val, &err);
  259. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
  260. if (on) {
  261. /* device WAKEUP through KSO:
  262. @@ -724,7 +723,7 @@ brcmf_sdio_kso_control(struct brcmf_sdio
  263. * just one write attempt may fail,
  264. * read it back until it matches written value
  265. */
  266. - rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  267. + rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  268. &err);
  269. if (!err) {
  270. if ((rd_val & bmask) == cmp_val)
  271. @@ -734,9 +733,11 @@ brcmf_sdio_kso_control(struct brcmf_sdio
  272. /* bail out upon subsequent access errors */
  273. if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS))
  274. break;
  275. +
  276. udelay(KSO_WAIT_US);
  277. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  278. - wr_val, &err);
  279. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val,
  280. + &err);
  281. +
  282. } while (try_cnt++ < MAX_KSO_ATTEMPTS);
  283. if (try_cnt > 2)
  284. @@ -772,15 +773,15 @@ static int brcmf_sdio_htclk(struct brcmf
  285. clkreq =
  286. bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
  287. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  288. - clkreq, &err);
  289. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  290. + clkreq, &err);
  291. if (err) {
  292. brcmf_err("HT Avail request error: %d\n", err);
  293. return -EBADE;
  294. }
  295. /* Check current status */
  296. - clkctl = brcmf_sdiod_regrb(bus->sdiodev,
  297. + clkctl = brcmf_sdiod_readb(bus->sdiodev,
  298. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  299. if (err) {
  300. brcmf_err("HT Avail read error: %d\n", err);
  301. @@ -790,35 +791,34 @@ static int brcmf_sdio_htclk(struct brcmf
  302. /* Go to pending and await interrupt if appropriate */
  303. if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
  304. /* Allow only clock-available interrupt */
  305. - devctl = brcmf_sdiod_regrb(bus->sdiodev,
  306. + devctl = brcmf_sdiod_readb(bus->sdiodev,
  307. SBSDIO_DEVICE_CTL, &err);
  308. if (err) {
  309. - brcmf_err("Devctl error setting CA: %d\n",
  310. - err);
  311. + brcmf_err("Devctl error setting CA: %d\n", err);
  312. return -EBADE;
  313. }
  314. devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
  315. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  316. - devctl, &err);
  317. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  318. + devctl, &err);
  319. brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
  320. bus->clkstate = CLK_PENDING;
  321. return 0;
  322. } else if (bus->clkstate == CLK_PENDING) {
  323. /* Cancel CA-only interrupt filter */
  324. - devctl = brcmf_sdiod_regrb(bus->sdiodev,
  325. + devctl = brcmf_sdiod_readb(bus->sdiodev,
  326. SBSDIO_DEVICE_CTL, &err);
  327. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  328. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  329. - devctl, &err);
  330. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  331. + devctl, &err);
  332. }
  333. /* Otherwise, wait here (polling) for HT Avail */
  334. timeout = jiffies +
  335. msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
  336. while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  337. - clkctl = brcmf_sdiod_regrb(bus->sdiodev,
  338. + clkctl = brcmf_sdiod_readb(bus->sdiodev,
  339. SBSDIO_FUNC1_CHIPCLKCSR,
  340. &err);
  341. if (time_after(jiffies, timeout))
  342. @@ -852,16 +852,16 @@ static int brcmf_sdio_htclk(struct brcmf
  343. if (bus->clkstate == CLK_PENDING) {
  344. /* Cancel CA-only interrupt filter */
  345. - devctl = brcmf_sdiod_regrb(bus->sdiodev,
  346. + devctl = brcmf_sdiod_readb(bus->sdiodev,
  347. SBSDIO_DEVICE_CTL, &err);
  348. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  349. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  350. - devctl, &err);
  351. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  352. + devctl, &err);
  353. }
  354. bus->clkstate = CLK_SDONLY;
  355. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  356. - clkreq, &err);
  357. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  358. + clkreq, &err);
  359. brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
  360. if (err) {
  361. brcmf_err("Failed access turning clock off: %d\n",
  362. @@ -951,14 +951,14 @@ brcmf_sdio_bus_sleep(struct brcmf_sdio *
  363. /* Going to sleep */
  364. if (sleep) {
  365. - clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
  366. + clkcsr = brcmf_sdiod_readb(bus->sdiodev,
  367. SBSDIO_FUNC1_CHIPCLKCSR,
  368. &err);
  369. if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
  370. brcmf_dbg(SDIO, "no clock, set ALP\n");
  371. - brcmf_sdiod_regwb(bus->sdiodev,
  372. - SBSDIO_FUNC1_CHIPCLKCSR,
  373. - SBSDIO_ALP_AVAIL_REQ, &err);
  374. + brcmf_sdiod_writeb(bus->sdiodev,
  375. + SBSDIO_FUNC1_CHIPCLKCSR,
  376. + SBSDIO_ALP_AVAIL_REQ, &err);
  377. }
  378. err = brcmf_sdio_kso_control(bus, false);
  379. } else {
  380. @@ -1178,16 +1178,16 @@ static void brcmf_sdio_rxfail(struct brc
  381. if (abort)
  382. brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
  383. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
  384. - SFC_RF_TERM, &err);
  385. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
  386. + &err);
  387. bus->sdcnt.f1regdata++;
  388. /* Wait until the packet has been flushed (device/FIFO stable) */
  389. for (lastrbc = retries = 0xffff; retries > 0; retries--) {
  390. - hi = brcmf_sdiod_regrb(bus->sdiodev,
  391. - SBSDIO_FUNC1_RFRAMEBCHI, &err);
  392. - lo = brcmf_sdiod_regrb(bus->sdiodev,
  393. - SBSDIO_FUNC1_RFRAMEBCLO, &err);
  394. + hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI,
  395. + &err);
  396. + lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO,
  397. + &err);
  398. bus->sdcnt.f1regdata += 2;
  399. if ((hi == 0) && (lo == 0))
  400. @@ -1229,12 +1229,12 @@ static void brcmf_sdio_txfail(struct brc
  401. bus->sdcnt.tx_sderrs++;
  402. brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
  403. - brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
  404. + brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
  405. bus->sdcnt.f1regdata++;
  406. for (i = 0; i < 3; i++) {
  407. - hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
  408. - lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
  409. + hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
  410. + lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
  411. bus->sdcnt.f1regdata += 2;
  412. if ((hi == 0) && (lo == 0))
  413. break;
  414. @@ -2446,11 +2446,11 @@ static void brcmf_sdio_bus_stop(struct d
  415. bus->hostintmask = 0;
  416. /* Force backplane clocks to assure F2 interrupt propagates */
  417. - saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  418. + saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  419. &err);
  420. if (!err)
  421. - brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  422. - (saveclk | SBSDIO_FORCE_HT), &err);
  423. + brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  424. + (saveclk | SBSDIO_FORCE_HT), &err);
  425. if (err)
  426. brcmf_err("Failed to force clock for F2: err %d\n",
  427. err);
  428. @@ -2509,7 +2509,7 @@ static int brcmf_sdio_intr_rstatus(struc
  429. buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
  430. addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
  431. - val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
  432. + val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret);
  433. bus->sdcnt.f1regdata++;
  434. if (ret != 0)
  435. return ret;
  436. @@ -2519,7 +2519,7 @@ static int brcmf_sdio_intr_rstatus(struc
  437. /* Clear interrupts */
  438. if (val) {
  439. - brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
  440. + brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret);
  441. bus->sdcnt.f1regdata++;
  442. atomic_or(val, &bus->intstatus);
  443. }
  444. @@ -2545,23 +2545,23 @@ static void brcmf_sdio_dpc(struct brcmf_
  445. #ifdef DEBUG
  446. /* Check for inconsistent device control */
  447. - devctl = brcmf_sdiod_regrb(bus->sdiodev,
  448. - SBSDIO_DEVICE_CTL, &err);
  449. + devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  450. + &err);
  451. #endif /* DEBUG */
  452. /* Read CSR, if clock on switch to AVAIL, else ignore */
  453. - clkctl = brcmf_sdiod_regrb(bus->sdiodev,
  454. + clkctl = brcmf_sdiod_readb(bus->sdiodev,
  455. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  456. brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
  457. devctl, clkctl);
  458. if (SBSDIO_HTAV(clkctl)) {
  459. - devctl = brcmf_sdiod_regrb(bus->sdiodev,
  460. + devctl = brcmf_sdiod_readb(bus->sdiodev,
  461. SBSDIO_DEVICE_CTL, &err);
  462. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  463. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
  464. - devctl, &err);
  465. + brcmf_sdiod_writeb(bus->sdiodev,
  466. + SBSDIO_DEVICE_CTL, devctl, &err);
  467. bus->clkstate = CLK_AVAIL;
  468. }
  469. }
  470. @@ -3347,31 +3347,31 @@ static void brcmf_sdio_sr_init(struct br
  471. brcmf_dbg(TRACE, "Enter\n");
  472. - val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
  473. + val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
  474. if (err) {
  475. brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
  476. return;
  477. }
  478. val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
  479. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
  480. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
  481. if (err) {
  482. brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
  483. return;
  484. }
  485. /* Add CMD14 Support */
  486. - brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
  487. - (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
  488. - SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
  489. - &err);
  490. + brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
  491. + (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
  492. + SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
  493. + &err);
  494. if (err) {
  495. brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
  496. return;
  497. }
  498. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  499. - SBSDIO_FORCE_HT, &err);
  500. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  501. + SBSDIO_FORCE_HT, &err);
  502. if (err) {
  503. brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
  504. return;
  505. @@ -3394,7 +3394,7 @@ static int brcmf_sdio_kso_init(struct br
  506. if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
  507. return 0;
  508. - val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
  509. + val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
  510. if (err) {
  511. brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
  512. return err;
  513. @@ -3403,8 +3403,8 @@ static int brcmf_sdio_kso_init(struct br
  514. if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
  515. val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
  516. SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
  517. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  518. - val, &err);
  519. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
  520. + val, &err);
  521. if (err) {
  522. brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
  523. return err;
  524. @@ -3565,9 +3565,9 @@ static void brcmf_sdio_bus_watchdog(stru
  525. u8 devpend;
  526. sdio_claim_host(bus->sdiodev->func[1]);
  527. - devpend = brcmf_sdiod_regrb(bus->sdiodev,
  528. - SDIO_CCCR_INTx,
  529. - NULL);
  530. + devpend = brcmf_sdiod_func0_rb(bus->sdiodev,
  531. + SDIO_CCCR_INTx,
  532. + NULL);
  533. sdio_release_host(bus->sdiodev->func[1]);
  534. intstatus = devpend & (INTR_STATUS_FUNC1 |
  535. INTR_STATUS_FUNC2);
  536. @@ -3705,12 +3705,12 @@ brcmf_sdio_drivestrengthinit(struct brcm
  537. }
  538. }
  539. addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
  540. - brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
  541. - cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
  542. + brcmf_sdiod_writel(sdiodev, addr, 1, NULL);
  543. + cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL);
  544. cc_data_temp &= ~str_mask;
  545. drivestrength_sel <<= str_shift;
  546. cc_data_temp |= drivestrength_sel;
  547. - brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
  548. + brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL);
  549. brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
  550. str_tab[i].strength, drivestrength, cc_data_temp);
  551. @@ -3725,7 +3725,7 @@ static int brcmf_sdio_buscoreprep(void *
  552. /* Try forcing SDIO core to do ALPAvail request only */
  553. clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
  554. - brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
  555. + brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
  556. if (err) {
  557. brcmf_err("error writing for HT off\n");
  558. return err;
  559. @@ -3733,8 +3733,7 @@ static int brcmf_sdio_buscoreprep(void *
  560. /* If register supported, wait for ALPAvail and then force ALP */
  561. /* This may take up to 15 milliseconds */
  562. - clkval = brcmf_sdiod_regrb(sdiodev,
  563. - SBSDIO_FUNC1_CHIPCLKCSR, NULL);
  564. + clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL);
  565. if ((clkval & ~SBSDIO_AVBITS) != clkset) {
  566. brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
  567. @@ -3742,10 +3741,11 @@ static int brcmf_sdio_buscoreprep(void *
  568. return -EACCES;
  569. }
  570. - SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
  571. - SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
  572. - !SBSDIO_ALPAV(clkval)),
  573. - PMU_MAX_TRANSITION_DLY);
  574. + SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  575. + NULL)),
  576. + !SBSDIO_ALPAV(clkval)),
  577. + PMU_MAX_TRANSITION_DLY);
  578. +
  579. if (!SBSDIO_ALPAV(clkval)) {
  580. brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
  581. clkval);
  582. @@ -3753,11 +3753,11 @@ static int brcmf_sdio_buscoreprep(void *
  583. }
  584. clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
  585. - brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
  586. + brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
  587. udelay(65);
  588. /* Also, disable the extra SDIO pull-ups */
  589. - brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
  590. + brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
  591. return 0;
  592. }
  593. @@ -3772,7 +3772,7 @@ static void brcmf_sdio_buscore_activate(
  594. /* clear all interrupts */
  595. core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
  596. reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
  597. - brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
  598. + brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
  599. if (rstvec)
  600. /* Write reset vector to address 0 */
  601. @@ -3785,7 +3785,7 @@ static u32 brcmf_sdio_buscore_read32(voi
  602. struct brcmf_sdio_dev *sdiodev = ctx;
  603. u32 val, rev;
  604. - val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
  605. + val = brcmf_sdiod_readl(sdiodev, addr, NULL);
  606. if ((sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 ||
  607. sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4339) &&
  608. addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
  609. @@ -3802,7 +3802,7 @@ static void brcmf_sdio_buscore_write32(v
  610. {
  611. struct brcmf_sdio_dev *sdiodev = ctx;
  612. - brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
  613. + brcmf_sdiod_writel(sdiodev, addr, val, NULL);
  614. }
  615. static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
  616. @@ -3826,18 +3826,18 @@ brcmf_sdio_probe_attach(struct brcmf_sdi
  617. sdio_claim_host(sdiodev->func[1]);
  618. pr_debug("F1 signature read @0x18000000=0x%4x\n",
  619. - brcmf_sdiod_regrl(sdiodev, SI_ENUM_BASE, NULL));
  620. + brcmf_sdiod_readl(sdiodev, SI_ENUM_BASE, NULL));
  621. /*
  622. * Force PLL off until brcmf_chip_attach()
  623. * programs PLL control regs
  624. */
  625. - brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  626. - BRCMF_INIT_CLKCTL1, &err);
  627. + brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1,
  628. + &err);
  629. if (!err)
  630. - clkctl = brcmf_sdiod_regrb(sdiodev,
  631. - SBSDIO_FUNC1_CHIPCLKCSR, &err);
  632. + clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  633. + &err);
  634. if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
  635. brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
  636. @@ -3897,25 +3897,25 @@ brcmf_sdio_probe_attach(struct brcmf_sdi
  637. brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
  638. /* Set card control so an SDIO card reset does a WLAN backplane reset */
  639. - reg_val = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
  640. + reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
  641. if (err)
  642. goto fail;
  643. reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
  644. - brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
  645. + brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
  646. if (err)
  647. goto fail;
  648. /* set PMUControl so a backplane reset does PMU state reload */
  649. reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
  650. - reg_val = brcmf_sdiod_regrl(sdiodev, reg_addr, &err);
  651. + reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err);
  652. if (err)
  653. goto fail;
  654. reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
  655. - brcmf_sdiod_regwl(sdiodev, reg_addr, reg_val, &err);
  656. + brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err);
  657. if (err)
  658. goto fail;
  659. @@ -4055,10 +4055,10 @@ static void brcmf_sdio_firmware_callback
  660. goto release;
  661. /* Force clocks on backplane to be sure F2 interrupt propagates */
  662. - saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
  663. + saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
  664. if (!err) {
  665. - brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  666. - (saveclk | SBSDIO_FORCE_HT), &err);
  667. + brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  668. + (saveclk | SBSDIO_FORCE_HT), &err);
  669. }
  670. if (err) {
  671. brcmf_err("Failed to force clock for F2: err %d\n", err);
  672. @@ -4080,7 +4080,7 @@ static void brcmf_sdio_firmware_callback
  673. w_sdreg32(bus, bus->hostintmask,
  674. offsetof(struct sdpcmd_regs, hostintmask));
  675. - brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
  676. + brcmf_sdiod_writeb(sdiodev, SBSDIO_WATERMARK, 8, &err);
  677. } else {
  678. /* Disable F2 again */
  679. sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
  680. @@ -4091,8 +4091,8 @@ static void brcmf_sdio_firmware_callback
  681. brcmf_sdio_sr_init(bus);
  682. } else {
  683. /* Restore previous clock setting */
  684. - brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  685. - saveclk, &err);
  686. + brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
  687. + saveclk, &err);
  688. }
  689. if (err == 0) {
  690. @@ -4225,7 +4225,7 @@ struct brcmf_sdio *brcmf_sdio_probe(stru
  691. bus->rxflow = false;
  692. /* Done with backplane-dependent accesses, can drop clock... */
  693. - brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  694. + brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  695. sdio_release_host(bus->sdiodev->func[1]);
  696. --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h
  697. +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.h
  698. @@ -50,6 +50,7 @@
  699. #define SBSDIO_NUM_FUNCTION 3
  700. /* function 0 vendor specific CCCR registers */
  701. +
  702. #define SDIO_CCCR_BRCM_CARDCAP 0xf0
  703. #define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
  704. #define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
  705. @@ -131,8 +132,6 @@
  706. /* with b15, maps to 32-bit SB access */
  707. #define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
  708. -/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
  709. -
  710. /* Address bits from SBADDR regs */
  711. #define SBSDIO_SBWINDOW_MASK 0xffff8000
  712. @@ -293,13 +292,24 @@ struct sdpcmd_regs {
  713. int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev);
  714. void brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev);
  715. -/* sdio device register access interface */
  716. -u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
  717. -u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
  718. -void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr, u8 data,
  719. - int *ret);
  720. -void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
  721. - int *ret);
  722. +/* SDIO device register access interface */
  723. +/* Accessors for SDIO Function 0 */
  724. +#define brcmf_sdiod_func0_rb(sdiodev, addr, r) \
  725. + sdio_readb((sdiodev)->func[0], (addr), (r))
  726. +
  727. +#define brcmf_sdiod_func0_wb(sdiodev, addr, v, ret) \
  728. + sdio_writeb((sdiodev)->func[0], (v), (addr), (ret))
  729. +
  730. +/* Accessors for SDIO Function 1 */
  731. +#define brcmf_sdiod_readb(sdiodev, addr, r) \
  732. + sdio_readb((sdiodev)->func[1], (addr), (r))
  733. +
  734. +#define brcmf_sdiod_writeb(sdiodev, addr, v, ret) \
  735. + sdio_writeb((sdiodev)->func[1], (v), (addr), (ret))
  736. +
  737. +u32 brcmf_sdiod_readl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
  738. +void brcmf_sdiod_writel(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
  739. + int *ret);
  740. /* Buffer transfer to/from device (client) core via cmd53.
  741. * fn: function number