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bcm6368-interrupt-controller.h 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. #ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H
  3. #define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H
  4. #define BCM6368_IRQ_TIMER 0
  5. #define BCM6368_IRQ_SPI 1
  6. #define BCM6368_IRQ_UART0 2
  7. #define BCM6368_IRQ_UART1 3
  8. #define BCM6368_IRQ_XDSL 4
  9. #define BCM6368_IRQ_OHCI 5
  10. #define BCM6368_IRQ_IPSEC 6
  11. #define BCM6368_IRQ_EHCI 7
  12. #define BCM6368_IRQ_USBS 8
  13. #define BCM6368_IRQ_RING_OSC 9
  14. #define BCM6368_IRQ_NAND 10
  15. #define BCM6368_IRQ_ATM 11
  16. #define BCM6368_IRQ_PCM 12
  17. #define BCM6368_IRQ_MPI 13
  18. #define BCM6368_IRQ_DG 14
  19. #define BCM6368_IRQ_EPHY 15
  20. #define BCM6368_IRQ_EPHY_EN0 16
  21. #define BCM6368_IRQ_EPHY_EN1 17
  22. #define BCM6368_IRQ_EPHY_EN2 18
  23. #define BCM6368_IRQ_EPHY_EN3 19
  24. #define BCM6368_IRQ_EXT0 20
  25. #define BCM6368_IRQ_EXT1 21
  26. #define BCM6368_IRQ_EXT2 22
  27. #define BCM6368_IRQ_EXT3 23
  28. #define BCM6368_IRQ_EXT4 24
  29. #define BCM6368_IRQ_EXT5 25
  30. #define BCM6368_IRQ_USB_CTL_RX_DMA 26
  31. #define BCM6368_IRQ_USB_CTL_TX_DMA 27
  32. #define BCM6368_IRQ_USB_BULK_RX_DMA 28
  33. #define BCM6368_IRQ_USB_BULK_TX_DMA 29
  34. #define BCM6368_IRQ_USB_ISO_RX_DMA 30
  35. #define BCM6368_IRQ_USB_ISO_TX_DMA 31
  36. #define BCM6368_IRQ_ENETSW_RX_DMA0 32
  37. #define BCM6368_IRQ_ENETSW_RX_DMA1 33
  38. #define BCM6368_IRQ_ENETSW_RX_DMA2 34
  39. #define BCM6368_IRQ_ENETSW_RX_DMA3 35
  40. #define BCM6368_IRQ_ENETSW_TX_DMA0 36
  41. #define BCM6368_IRQ_ENETSW_TX_DMA1 37
  42. #define BCM6368_IRQ_ENETSW_TX_DMA2 38
  43. #define BCM6368_IRQ_ENETSW_TX_DMA3 39
  44. #define BCM6368_IRQ_ATM_DMA0 40
  45. #define BCM6368_IRQ_ATM_DMA1 41
  46. #define BCM6368_IRQ_ATM_DMA2 42
  47. #define BCM6368_IRQ_ATM_DMA3 43
  48. #define BCM6368_IRQ_ATM_DMA4 44
  49. #define BCM6368_IRQ_ATM_DMA5 45
  50. #define BCM6368_IRQ_ATM_DMA6 46
  51. #define BCM6368_IRQ_ATM_DMA7 47
  52. #define BCM6368_IRQ_ATM_DMA8 48
  53. #define BCM6368_IRQ_ATM_DMA9 49
  54. #define BCM6368_IRQ_ATM_DMA10 50
  55. #define BCM6368_IRQ_ATM_DMA11 51
  56. #define BCM6368_IRQ_ATM_DMA12 52
  57. #define BCM6368_IRQ_ATM_DMA13 53
  58. #define BCM6368_IRQ_ATM_DMA14 54
  59. #define BCM6368_IRQ_ATM_DMA15 55
  60. #define BCM6368_IRQ_ATM_DMA16 56
  61. #define BCM6368_IRQ_ATM_DMA17 57
  62. #define BCM6368_IRQ_ATM_DMA18 58
  63. #define BCM6368_IRQ_ATM_DMA19 59
  64. #define BCM6368_IRQ_IPSEC_DMA0 60
  65. #define BCM6368_IRQ_IPSEC_DMA1 61
  66. #define BCM6368_IRQ_PCM_DMA0 62
  67. #define BCM6368_IRQ_PCM_DMA1 63
  68. #define BCM6368_EXTIRQ0_0 0 /* GPIO 34 */
  69. #define BCM6368_EXTIRQ0_1 1 /* GPIO 35 */
  70. #define BCM6368_EXTIRQ0_2 2 /* GPIO 36 */
  71. #define BCM6368_EXTIRQ0_3 3 /* GPIO 37 */
  72. #define BCM6368_EXTIRQ1_4 0 /* GPIO 32 */
  73. #define BCM6368_EXTIRQ1_5 1 /* GPIO 33 */
  74. #endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H */