openwrt/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ7362SL.dts

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;

#include "FRITZ736X.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/mips/lantiq_rcu_gphy.h>

/ {
	compatible = "avm,fritz7362sl", "avm,fritz736x", "lantiq,xway", "lantiq,vr9";
	model = "AVM FRITZ!Box 7362 SL";
};

&power_green {
	label = "fritz7362sl:green:power";
};

&power_red {
	label = "fritz7362sl:red:power";
};

&info_green {
	label = "fritz7362sl:green:info";
};

&wifi {
	label = "fritz7362sl:green:wlan";
};

&info_red {
	label = "fritz7362sl:red:info";
};

&dect {
	label = "fritz7362sl:green:dect";
};

&gpio {
	pins_spi_default: pins_spi_default {
		spi_in {
			lantiq,groups = "spi_di";
			lantiq,function = "spi";
		};

		spi_out {
			lantiq,groups = "spi_do", "spi_clk",
				"spi_cs4";
			lantiq,function = "spi";
			lantiq,output = <1>;
		};
	};
};

&state_default {
	nand {
		lantiq,groups = "nand ale", "nand cle",
				"nand cs1", "nand rd", "nand rdy";
		lantiq,function = "ebu";
	};

	pcie-rst {
		lantiq,pins = "io21";
		lantiq,open-drain = <1>;
		lantiq,output = <1>;
	};
};

&spi {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pins_spi_default>;

	flash@4 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <4 0>;
		spi-max-frequency = <1000000>;

		urlader: partition@0 {
			reg = <0x0 0x40000>;
			label = "urlader";
			read-only;
		};

		partition@40000 {
			reg = <0x40000 0x60000>;
			label = "tffs (1)";
			read-only;
		};

		partition@A0000 {
			reg = <0xA0000 0x60000>;
			label = "tffs (2)";
			read-only;
		};
	};
};

&localbus {
	nand@1 {
		compatible = "lantiq,nand-xway";
		lantiq,cs1 = <1>;
		bank-width = <1>;
		reg = <1 0x0 0x2000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		nand-ecc-mode = "on-die";

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "kernel";
				reg = <0x0 0x400000>;
			};

			partition@400000 {
				label = "ubi";
				reg = <0x400000 0x7c00000>;
			};
		};
	};
};

&pcie0 {
	gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;

	pcie@0 {
		#size-cells = <1>;
		#address-cells = <2>;
	};
};