qcom-ipq8062-wg2600hp3.dts 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq8062-smb208.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. model = "NEC Platforms Aterm WG2600HP3";
  6. compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064";
  7. memory {
  8. device_type = "memory";
  9. reg = <0x42000000 0x1e000000>;
  10. };
  11. aliases {
  12. label-mac-device = &gmac2;
  13. led-boot = &led_power_green;
  14. led-failsafe = &led_power_red;
  15. led-running = &led_power_green;
  16. led-upgrade = &led_power_red;
  17. };
  18. keys {
  19. compatible = "gpio-keys";
  20. pinctrl-0 = <&buttons_pins>;
  21. pinctrl-names = "default";
  22. reset {
  23. label = "reset";
  24. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
  25. linux,code = <KEY_RESTART>;
  26. debounce-interval = <60>;
  27. wakeup-source;
  28. };
  29. wps {
  30. label = "wps";
  31. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
  32. linux,code = <KEY_WPS_BUTTON>;
  33. debounce-interval = <60>;
  34. wakeup-source;
  35. };
  36. mode0 {
  37. label = "mode0";
  38. gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>;
  39. linux,code = <BTN_0>;
  40. linux,input-type = <EV_SW>;
  41. debounce-interval = <60>;
  42. wakeup-source;
  43. };
  44. mode1 {
  45. label = "mode1";
  46. gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>;
  47. linux,code = <BTN_1>;
  48. linux,input-type = <EV_SW>;
  49. debounce-interval = <60>;
  50. wakeup-source;
  51. };
  52. };
  53. leds {
  54. compatible = "gpio-leds";
  55. pinctrl-0 = <&leds_pins>;
  56. pinctrl-names = "default";
  57. led_power_green: power_green {
  58. label = "green:power";
  59. gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
  60. };
  61. led_power_red: power_red {
  62. label = "red:power";
  63. gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>;
  64. };
  65. active_green {
  66. label = "green:active";
  67. gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>;
  68. };
  69. active_red {
  70. label = "red:active";
  71. gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>;
  72. };
  73. wlan2g_green {
  74. label = "green:wlan2g";
  75. gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
  76. linux,default-trigger = "phy1tpt";
  77. };
  78. wlan2g_red {
  79. label = "red:wlan2g";
  80. gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
  81. };
  82. wlan5g_green {
  83. label = "green:wlan5g";
  84. gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
  85. linux,default-trigger = "phy0tpt";
  86. };
  87. wlan5g_red {
  88. label = "red:wlan5g";
  89. gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
  90. };
  91. tv_green {
  92. label = "green:tv";
  93. gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>;
  94. };
  95. tv_red {
  96. label = "red:tv";
  97. gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>;
  98. };
  99. converter_green {
  100. label = "green:converter";
  101. gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>;
  102. };
  103. converter_red {
  104. label = "red:converter";
  105. gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
  106. };
  107. };
  108. };
  109. /* nand_pins are used for leds_pins, empty the node
  110. * from ipq8064.dtsi
  111. */
  112. &nand_pins {
  113. /delete-property/ disable;
  114. /delete-property/ pullups;
  115. /delete-property/ hold;
  116. };
  117. &qcom_pinmux {
  118. pinctrl-0 = <&akro_pins>;
  119. pinctrl-names = "default";
  120. spi_pins: spi_pins {
  121. mux {
  122. pins = "gpio18", "gpio19", "gpio21";
  123. function = "gsbi5";
  124. bias-pull-down;
  125. };
  126. data {
  127. pins = "gpio18", "gpio19";
  128. drive-strength = <10>;
  129. };
  130. cs {
  131. pins = "gpio20";
  132. drive-strength = <10>;
  133. };
  134. clk {
  135. pins = "gpio21";
  136. drive-strength = <12>;
  137. };
  138. };
  139. buttons_pins: buttons_pins {
  140. mux {
  141. pins = "gpio22", "gpio24", "gpio40",
  142. "gpio41";
  143. function = "gpio";
  144. drive-strength = <2>;
  145. bias-pull-up;
  146. };
  147. };
  148. leds_pins: leds_pins {
  149. mux {
  150. pins = "gpio14", "gpio15", "gpio35",
  151. "gpio36", "gpio38", "gpio42",
  152. "gpio43", "gpio46", "gpio55",
  153. "gpio56", "gpio57", "gpio58";
  154. function = "gpio";
  155. bias-pull-down;
  156. };
  157. akro2 {
  158. pins = "gpio15", "gpio35", "gpio38",
  159. "gpio42", "gpio43", "gpio46",
  160. "gpio55", "gpio56", "gpio57",
  161. "gpio58";
  162. drive-strength = <2>;
  163. };
  164. akro4 {
  165. pins = "gpio14", "gpio36";
  166. drive-strength = <4>;
  167. };
  168. };
  169. /*
  170. * Stock firmware has the following settings, so let's do the same.
  171. * I don't sure why these are required.
  172. */
  173. akro_pins: akro_pinmux {
  174. akro {
  175. pins = "gpio17", "gpio26", "gpio47";
  176. function = "gpio";
  177. drive-strength = <2>;
  178. bias-pull-down;
  179. };
  180. reset {
  181. pins = "gpio45";
  182. function = "gpio";
  183. drive-strength = <2>;
  184. bias-disable;
  185. output-low;
  186. };
  187. gmac0_rgmii {
  188. pins = "gpio25";
  189. function = "gpio";
  190. drive-strength = <8>;
  191. bias-disable;
  192. };
  193. };
  194. };
  195. &gsbi5 {
  196. status = "okay";
  197. qcom,mode = <GSBI_PROT_SPI>;
  198. spi@1a280000 {
  199. status = "okay";
  200. pinctrl-0 = <&spi_pins>;
  201. pinctrl-names = "default";
  202. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  203. flash@0 {
  204. compatible = "jedec,spi-nor";
  205. reg = <0>;
  206. spi-max-frequency = <50000000>;
  207. m25p,fast-read;
  208. partitions {
  209. compatible = "fixed-partitions";
  210. #address-cells = <1>;
  211. #size-cells = <1>;
  212. partition@0 {
  213. label = "SBL1";
  214. reg = <0x0000000 0x0020000>;
  215. read-only;
  216. };
  217. partition@20000 {
  218. label = "MIBIB";
  219. reg = <0x0020000 0x0020000>;
  220. read-only;
  221. };
  222. partition@40000 {
  223. label = "SBL2";
  224. reg = <0x0040000 0x0040000>;
  225. read-only;
  226. };
  227. partition@80000 {
  228. label = "SBL3";
  229. reg = <0x0080000 0x0080000>;
  230. read-only;
  231. };
  232. partition@100000 {
  233. label = "DDRCONFIG";
  234. reg = <0x0100000 0x0010000>;
  235. read-only;
  236. };
  237. partition@110000 {
  238. label = "SSD";
  239. reg = <0x0110000 0x0010000>;
  240. read-only;
  241. };
  242. partition@120000 {
  243. label = "TZ";
  244. reg = <0x0120000 0x0080000>;
  245. read-only;
  246. };
  247. partition@1a0000 {
  248. label = "RPM";
  249. reg = <0x01a0000 0x0080000>;
  250. read-only;
  251. };
  252. partition@220000 {
  253. label = "APPSBL";
  254. reg = <0x0220000 0x0080000>;
  255. read-only;
  256. };
  257. partition@2a0000 {
  258. label = "APPSBLENV";
  259. reg = <0x02a0000 0x0010000>;
  260. read-only;
  261. };
  262. factory: partition@2b0000 {
  263. label = "PRODUCTDATA";
  264. reg = <0x02b0000 0x0030000>;
  265. read-only;
  266. };
  267. partition@2e0000 {
  268. label = "ART";
  269. reg = <0x02e0000 0x0040000>;
  270. read-only;
  271. compatible = "nvmem-cells";
  272. #address-cells = <1>;
  273. #size-cells = <1>;
  274. precal_ART_1000: precal@1000 {
  275. reg = <0x1000 0x2f20>;
  276. };
  277. precal_ART_5000: precal@5000 {
  278. reg = <0x5000 0x2f20>;
  279. };
  280. };
  281. partition@320000 {
  282. label = "TP";
  283. reg = <0x0320000 0x0040000>;
  284. read-only;
  285. };
  286. partition@360000 {
  287. label = "TINY";
  288. reg = <0x0360000 0x0500000>;
  289. read-only;
  290. };
  291. partition@860000 {
  292. compatible = "denx,uimage";
  293. label = "firmware";
  294. reg = <0x0860000 0x17a0000>;
  295. };
  296. };
  297. };
  298. };
  299. };
  300. &adm_dma {
  301. status = "okay";
  302. };
  303. &pcie0 {
  304. status = "okay";
  305. bridge@0,0 {
  306. reg = <0x00000000 0 0 0 0>;
  307. #address-cells = <3>;
  308. #size-cells = <2>;
  309. ranges;
  310. wifi@1,0 {
  311. compatible = "qcom,ath10k";
  312. reg = <0x00010000 0 0 0 0>;
  313. qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
  314. nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
  315. nvmem-cell-names = "mac-address", "pre-calibration";
  316. };
  317. };
  318. };
  319. &pcie1 {
  320. status = "okay";
  321. force_gen1 = <1>;
  322. bridge@0,0 {
  323. reg = <0x00000000 0 0 0 0>;
  324. #address-cells = <3>;
  325. #size-cells = <2>;
  326. ranges;
  327. wifi@1,0 {
  328. compatible = "qcom,ath10k";
  329. reg = <0x00010000 0 0 0 0>;
  330. ieee80211-freq-limit = <2400000 2483000>;
  331. qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
  332. nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
  333. nvmem-cell-names = "mac-address", "pre-calibration";
  334. };
  335. };
  336. };
  337. &mdio0 {
  338. status = "okay";
  339. pinctrl-0 = <&mdio0_pins>;
  340. pinctrl-names = "default";
  341. phy0: ethernet-phy@0 {
  342. reg = <0>;
  343. qca,ar8327-initvals = <
  344. 0x04 0x80080080 /* PAD0_MODE */
  345. 0x0c 0x06000000 /* PAD6_MODE */
  346. 0x10 0x002613a0 /* PWS_REG */
  347. 0x50 0xcc36cc36 /* LED_CTRL0 */
  348. 0x54 0xca36ca36 /* LED_CTRL1 */
  349. 0x58 0xc936c936 /* LED_CTRL2 */
  350. 0x5c 0x03ffff00 /* LED_CTRL3 */
  351. 0x7c 0x0000004e /* PORT0_STATUS */
  352. 0x94 0x0000004e /* PORT6_STATUS */
  353. 0xe0 0xc74164de /* SGMII_CTRL */
  354. 0xe4 0x0006a545 /* MAC_PWR_SEL */
  355. >;
  356. };
  357. };
  358. &gmac1 {
  359. status = "okay";
  360. pinctrl-0 = <&rgmii2_pins>;
  361. pinctrl-names = "default";
  362. phy-mode = "rgmii";
  363. qcom,id = <1>;
  364. mdiobus = <&mdio0>;
  365. nvmem-cells = <&macaddr_factory_0>;
  366. nvmem-cell-names = "mac-address";
  367. fixed-link {
  368. speed = <1000>;
  369. full-duplex;
  370. };
  371. };
  372. &gmac2 {
  373. status = "okay";
  374. phy-mode = "sgmii";
  375. qcom,id = <2>;
  376. mdiobus = <&mdio0>;
  377. nvmem-cells = <&macaddr_factory_6>;
  378. nvmem-cell-names = "mac-address";
  379. fixed-link {
  380. speed = <1000>;
  381. full-duplex;
  382. };
  383. };
  384. &factory {
  385. compatible = "nvmem-cells";
  386. #address-cells = <1>;
  387. #size-cells = <1>;
  388. macaddr_factory_0: macaddr@0 {
  389. reg = <0x0 0x6>;
  390. };
  391. macaddr_factory_6: macaddr@6 {
  392. reg = <0x6 0x6>;
  393. };
  394. macaddr_PRODUCTDATA_c: macaddr@c {
  395. reg = <0xc 0x6>;
  396. };
  397. macaddr_PRODUCTDATA_12: macaddr@12 {
  398. reg = <0x12 0x6>;
  399. };
  400. };
  401. &hs_phy_0 {
  402. status = "okay";
  403. };
  404. &ss_phy_0 {
  405. status = "okay";
  406. };
  407. &usb3_0 {
  408. status = "okay";
  409. };
  410. &hs_phy_1 {
  411. status = "okay";
  412. };
  413. &ss_phy_1 {
  414. status = "okay";
  415. };
  416. &usb3_1 {
  417. status = "okay";
  418. };