qcom-ipq8064-d7800.dts 6.5 KB

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  1. #include "qcom-ipq8064-v2.0-smb208.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. / {
  4. model = "Netgear Nighthawk X4 D7800";
  5. compatible = "netgear,d7800", "qcom,ipq8064";
  6. memory@0 {
  7. reg = <0x42000000 0x1e000000>;
  8. device_type = "memory";
  9. };
  10. reserved-memory {
  11. rsvd@5fe00000 {
  12. reg = <0x5fe00000 0x200000>;
  13. reusable;
  14. };
  15. };
  16. aliases {
  17. mdio-gpio0 = &mdio0;
  18. led-boot = &power_white;
  19. led-failsafe = &power_amber;
  20. led-running = &power_white;
  21. led-upgrade = &power_amber;
  22. };
  23. chosen {
  24. bootargs = "rootfstype=squashfs noinitrd";
  25. };
  26. keys {
  27. compatible = "gpio-keys";
  28. pinctrl-0 = <&button_pins>;
  29. pinctrl-names = "default";
  30. wifi {
  31. label = "wifi";
  32. gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
  33. linux,code = <KEY_RFKILL>;
  34. debounce-interval = <60>;
  35. wakeup-source;
  36. };
  37. reset {
  38. label = "reset";
  39. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  40. linux,code = <KEY_RESTART>;
  41. debounce-interval = <60>;
  42. wakeup-source;
  43. };
  44. wps {
  45. label = "wps";
  46. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  47. linux,code = <KEY_WPS_BUTTON>;
  48. debounce-interval = <60>;
  49. wakeup-source;
  50. };
  51. };
  52. leds {
  53. compatible = "gpio-leds";
  54. pinctrl-0 = <&led_pins>;
  55. pinctrl-names = "default";
  56. usb1 {
  57. label = "white:usb1";
  58. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  59. };
  60. usb2 {
  61. label = "white:usb2";
  62. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  63. };
  64. power_amber: power_amber {
  65. label = "amber:power";
  66. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  67. };
  68. wan_white {
  69. label = "white:wan";
  70. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  71. };
  72. wan_amber {
  73. label = "amber:wan";
  74. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  75. };
  76. wps {
  77. label = "white:wps";
  78. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  79. };
  80. esata {
  81. label = "white:esata";
  82. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
  83. };
  84. power_white: power_white {
  85. label = "white:power";
  86. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
  87. default-state = "keep";
  88. };
  89. wifi {
  90. label = "white:wifi";
  91. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
  92. };
  93. };
  94. };
  95. &qcom_pinmux {
  96. button_pins: button_pins {
  97. mux {
  98. pins = "gpio6", "gpio54", "gpio65";
  99. function = "gpio";
  100. drive-strength = <2>;
  101. bias-pull-up;
  102. };
  103. };
  104. led_pins: led_pins {
  105. mux {
  106. pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
  107. "gpio24","gpio26", "gpio53", "gpio64";
  108. function = "gpio";
  109. drive-strength = <2>;
  110. bias-pull-up;
  111. };
  112. };
  113. usb0_pwr_en_pins: usb0_pwr_en_pins {
  114. mux {
  115. pins = "gpio15";
  116. function = "gpio";
  117. drive-strength = <12>;
  118. bias-pull-down;
  119. output-high;
  120. };
  121. };
  122. usb1_pwr_en_pins: usb1_pwr_en_pins {
  123. mux {
  124. pins = "gpio16", "gpio68";
  125. function = "gpio";
  126. drive-strength = <12>;
  127. bias-pull-down;
  128. output-high;
  129. };
  130. };
  131. };
  132. &sata_phy {
  133. status = "okay";
  134. };
  135. &sata {
  136. status = "okay";
  137. };
  138. &hs_phy_0 {
  139. status = "okay";
  140. };
  141. &ss_phy_0 {
  142. status = "okay";
  143. };
  144. &usb3_0 {
  145. status = "okay";
  146. pinctrl-0 = <&usb0_pwr_en_pins>;
  147. pinctrl-names = "default";
  148. };
  149. &hs_phy_1 {
  150. status = "okay";
  151. };
  152. &ss_phy_1 {
  153. status = "okay";
  154. };
  155. &usb3_1 {
  156. status = "okay";
  157. pinctrl-0 = <&usb1_pwr_en_pins>;
  158. pinctrl-names = "default";
  159. };
  160. &pcie0 {
  161. status = "okay";
  162. reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
  163. pinctrl-0 = <&pcie0_pins>;
  164. pinctrl-names = "default";
  165. bridge@0,0 {
  166. reg = <0x00000000 0 0 0 0>;
  167. #address-cells = <3>;
  168. #size-cells = <2>;
  169. ranges;
  170. wifi@1,0 {
  171. compatible = "pci168c,0040";
  172. reg = <0x00010000 0 0 0 0>;
  173. nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;
  174. nvmem-cell-names = "mac-address", "pre-calibration";
  175. mac-address-increment = <(1)>;
  176. };
  177. };
  178. };
  179. &pcie1 {
  180. status = "okay";
  181. reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
  182. pinctrl-0 = <&pcie1_pins>;
  183. pinctrl-names = "default";
  184. max-link-speed = <1>;
  185. bridge@0,0 {
  186. reg = <0x00000000 0 0 0 0>;
  187. #address-cells = <3>;
  188. #size-cells = <2>;
  189. ranges;
  190. wifi@1,0 {
  191. compatible = "pci168c,0040";
  192. reg = <0x00010000 0 0 0 0>;
  193. nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;
  194. nvmem-cell-names = "mac-address", "pre-calibration";
  195. mac-address-increment = <(2)>;
  196. };
  197. };
  198. };
  199. &pcie2 {
  200. status = "okay";
  201. reset-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
  202. pinctrl-0 = <&pcie2_pins>;
  203. pinctrl-names = "default";
  204. };
  205. &nand {
  206. status = "okay";
  207. nand@0 {
  208. reg = <0>;
  209. compatible = "qcom,nandcs";
  210. nand-ecc-strength = <4>;
  211. nand-bus-width = <8>;
  212. nand-ecc-step-size = <512>;
  213. nand-is-boot-medium;
  214. qcom,boot-partitions = <0x0 0x1180000>;
  215. partitions {
  216. compatible = "fixed-partitions";
  217. #address-cells = <1>;
  218. #size-cells = <1>;
  219. qcadata@0 {
  220. label = "qcadata";
  221. reg = <0x0000000 0x0c80000>;
  222. read-only;
  223. };
  224. APPSBL@c80000 {
  225. label = "APPSBL";
  226. reg = <0x0c80000 0x0500000>;
  227. read-only;
  228. };
  229. APPSBLENV@1180000 {
  230. label = "APPSBLENV";
  231. reg = <0x1180000 0x0080000>;
  232. read-only;
  233. };
  234. art@1200000 {
  235. label = "art";
  236. reg = <0x1200000 0x0140000>;
  237. read-only;
  238. compatible = "nvmem-cells";
  239. #address-cells = <1>;
  240. #size-cells = <1>;
  241. macaddr_art_0: macaddr@0 {
  242. reg = <0x0 0x6>;
  243. };
  244. macaddr_art_6: macaddr@6 {
  245. reg = <0x6 0x6>;
  246. };
  247. precal_art_1000: precal@1000 {
  248. reg = <0x1000 0x2f20>;
  249. };
  250. precal_art_5000: precal@5000 {
  251. reg = <0x5000 0x2f20>;
  252. };
  253. };
  254. artbak: art@1340000 {
  255. label = "artbak";
  256. reg = <0x1340000 0x0140000>;
  257. read-only;
  258. };
  259. kernel@1480000 {
  260. label = "kernel";
  261. reg = <0x1480000 0x0400000>;
  262. };
  263. ubi@1880000 {
  264. label = "ubi";
  265. reg = <0x1880000 0x6080000>;
  266. };
  267. reserve@7900000 {
  268. label = "reserve";
  269. reg = <0x7900000 0x0700000>;
  270. read-only;
  271. };
  272. };
  273. };
  274. };
  275. &mdio0 {
  276. status = "okay";
  277. pinctrl-0 = <&mdio0_pins>;
  278. pinctrl-names = "default";
  279. phy0: ethernet-phy@0 {
  280. reg = <0>;
  281. qca,ar8327-initvals = <
  282. 0x00004 0x7600000 /* PAD0_MODE */
  283. 0x00008 0x1000000 /* PAD5_MODE */
  284. 0x0000c 0x80 /* PAD6_MODE */
  285. 0x000e4 0x6a545 /* MAC_POWER_SEL */
  286. 0x000e0 0xc74164de /* SGMII_CTRL */
  287. 0x0007c 0x4e /* PORT0_STATUS */
  288. 0x00094 0x4e /* PORT6_STATUS */
  289. >;
  290. };
  291. phy4: ethernet-phy@4 {
  292. reg = <4>;
  293. };
  294. };
  295. &gmac1 {
  296. status = "okay";
  297. phy-mode = "rgmii";
  298. qcom,id = <1>;
  299. pinctrl-0 = <&rgmii2_pins>;
  300. pinctrl-names = "default";
  301. nvmem-cells = <&macaddr_art_6>;
  302. nvmem-cell-names = "mac-address";
  303. fixed-link {
  304. speed = <1000>;
  305. full-duplex;
  306. };
  307. };
  308. &gmac2 {
  309. status = "okay";
  310. phy-mode = "sgmii";
  311. qcom,id = <2>;
  312. nvmem-cells = <&macaddr_art_0>;
  313. nvmem-cell-names = "mac-address";
  314. fixed-link {
  315. speed = <1000>;
  316. full-duplex;
  317. };
  318. };
  319. &adm_dma {
  320. status = "okay";
  321. };