qcom-ipq8064-g10.dts 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include "qcom-ipq8064-v2.0-smb208.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/soc/qcom,tcsr.h>
  5. / {
  6. compatible = "asrock,g10", "qcom,ipq8064";
  7. model = "ASRock G10";
  8. aliases {
  9. ethernet0 = &gmac1;
  10. ethernet1 = &gmac0;
  11. led-boot = &led_status_blue;
  12. led-failsafe = &led_status_amber;
  13. led-running = &led_status_blue;
  14. led-upgrade = &led_status_amber;
  15. };
  16. chosen {
  17. bootargs-override = "console=ttyMSM0,115200n8";
  18. };
  19. leds {
  20. compatible = "gpio-leds";
  21. pinctrl-0 = <&led_pins>;
  22. pinctrl-names = "default";
  23. /*
  24. * this is a bit misleading. Because there are about seven
  25. * multicolor LEDs connected all wired together in parallel.
  26. */
  27. status_yellow {
  28. label = "yellow:status";
  29. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  30. };
  31. led_status_amber: status_amber {
  32. label = "amber:status";
  33. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  34. };
  35. led_status_blue: status_blue {
  36. label = "blue:status";
  37. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  38. };
  39. /*
  40. * LED is declared in vendors boardfile but it's not
  41. * working and the manual doesn't mention anything
  42. * about the LED being white.
  43. status_white {
  44. label = "white:status";
  45. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
  46. };
  47. */
  48. };
  49. i2c-gpio {
  50. #address-cells = <1>;
  51. #size-cells = <0>;
  52. compatible = "i2c-gpio";
  53. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */
  54. <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */
  55. i2c-gpio,delay-us = <5>;
  56. i2c-gpio,scl-output-only;
  57. mcu@50 {
  58. reg = <0x50>;
  59. compatible = "sonix,sn8f25e21";
  60. };
  61. };
  62. keys {
  63. compatible = "gpio-keys";
  64. pinctrl-0 = <&button_pins>;
  65. pinctrl-names = "default";
  66. ir-remote {
  67. label = "ir-remote";
  68. gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
  69. linux,code = <BTN_0>;
  70. debounce-interval = <60>;
  71. wakeup-source;
  72. };
  73. reset {
  74. label = "reset";
  75. gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
  76. linux,code = <KEY_RESTART>;
  77. debounce-interval = <60>;
  78. wakeup-source;
  79. };
  80. wps5g {
  81. label = "wps5g";
  82. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
  83. linux,code = <KEY_WPS_BUTTON>;
  84. debounce-interval = <60>;
  85. wakeup-source;
  86. };
  87. wps2g {
  88. label = "wps2g";
  89. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  90. linux,code = <KEY_WPS_BUTTON>;
  91. debounce-interval = <60>;
  92. wakeup-source;
  93. };
  94. };
  95. };
  96. &adm_dma {
  97. status = "okay";
  98. };
  99. &gmac1 {
  100. status = "okay";
  101. pinctrl-0 = <&rgmii2_pins>;
  102. pinctrl-names = "default";
  103. phy-mode = "rgmii";
  104. qcom,id = <1>;
  105. fixed-link {
  106. speed = <1000>;
  107. full-duplex;
  108. };
  109. };
  110. &gmac2 {
  111. status = "okay";
  112. phy-mode = "sgmii";
  113. qcom,id = <2>;
  114. fixed-link {
  115. speed = <1000>;
  116. full-duplex;
  117. };
  118. };
  119. &gsbi4_serial {
  120. pinctrl-0 = <&uart0_pins>;
  121. pinctrl-names = "default";
  122. };
  123. &mdio0 {
  124. status = "okay";
  125. pinctrl-0 = <&mdio0_pins>;
  126. pinctrl-names = "default";
  127. ethernet-phy@0 {
  128. reg = <0>;
  129. qca,ar8327-initvals = <
  130. 0x00004 0x7600000 /* PAD0_MODE */
  131. 0x00008 0x1000000 /* PAD5_MODE */
  132. 0x0000c 0x80 /* PAD6_MODE */
  133. 0x000e4 0x6a545 /* MAC_POWER_SEL */
  134. 0x000e0 0xc74164de /* SGMII_CTRL */
  135. 0x0007c 0x4e /* PORT0_STATUS */
  136. 0x00094 0x4e /* PORT6_STATUS */
  137. >;
  138. };
  139. };
  140. &nand {
  141. status = "okay";
  142. nand@0 {
  143. reg = <0>;
  144. compatible = "qcom,nandcs";
  145. nand-ecc-strength = <4>;
  146. nand-bus-width = <8>;
  147. nand-ecc-step-size = <512>;
  148. nand-is-boot-medium;
  149. qcom,boot-partitions = <0x0 0x1200000>;
  150. partitions {
  151. compatible = "qcom,smem-part";
  152. };
  153. };
  154. };
  155. &pcie0 {
  156. status = "okay";
  157. bridge@0,0 {
  158. reg = <0x00000000 0 0 0 0>;
  159. #address-cells = <3>;
  160. #size-cells = <2>;
  161. ranges;
  162. wifi5g: wifi@1,0 {
  163. reg = <0x00010000 0 0 0 0>;
  164. compatible = "qcom,ath10k";
  165. qcom,ath10k-calibration-variant = "ASRock-G10";
  166. };
  167. };
  168. };
  169. &pcie1 {
  170. status = "okay";
  171. bridge@0,0 {
  172. reg = <0x00000000 0 0 0 0>;
  173. #address-cells = <3>;
  174. #size-cells = <2>;
  175. ranges;
  176. wifi2g: wifi@1,0 {
  177. reg = <0x00010000 0 0 0 0>;
  178. compatible = "qcom,ath10k";
  179. qcom,ath10k-calibration-variant = "ASRock-G10";
  180. };
  181. };
  182. };
  183. &qcom_pinmux {
  184. led_pins: led_pins {
  185. mux {
  186. pins = "gpio7", "gpio8", "gpio9", "gpio26";
  187. function = "gpio";
  188. drive-strength = <2>;
  189. bias-pull-up;
  190. };
  191. };
  192. button_pins: button_pins {
  193. mux {
  194. pins = "gpio15", "gpio16", "gpio64", "gpio65";
  195. function = "gpio";
  196. drive-strength = <2>;
  197. bias-pull-up;
  198. };
  199. };
  200. uart0_pins: uart0_pins {
  201. mux {
  202. pins = "gpio10", "gpio11";
  203. function = "gsbi4";
  204. drive-strength = <10>;
  205. bias-disable;
  206. };
  207. };
  208. };
  209. &rpm {
  210. pinctrl-0 = <&i2c4_pins>;
  211. pinctrl-names = "default";
  212. };
  213. &hs_phy_0 {
  214. status = "okay";
  215. };
  216. &ss_phy_0 {
  217. status = "okay";
  218. };
  219. &usb3_0 {
  220. status = "okay";
  221. };
  222. &hs_phy_1 {
  223. status = "okay";
  224. };
  225. &ss_phy_1 {
  226. status = "okay";
  227. };
  228. &usb3_1 {
  229. status = "okay";
  230. };
  231. &tcsr {
  232. qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
  233. };
  234. /delete-node/ &pcie2_pins;
  235. /delete-node/ &pcie2;