qcom-ipq8064-onhub.dtsi 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2014 The ChromiumOS Authors
  4. */
  5. #include "qcom-ipq8064-smb208.dtsi"
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/soc/qcom,tcsr.h>
  8. / {
  9. aliases {
  10. ethernet0 = &gmac0;
  11. ethernet1 = &gmac2;
  12. mdio-gpio0 = &mdio;
  13. serial0 = &gsbi4_serial;
  14. };
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. reserved-memory {
  19. #address-cells = <1>;
  20. #size-cells = <1>;
  21. ranges;
  22. rsvd@41200000 {
  23. reg = <0x41200000 0x300000>;
  24. no-map;
  25. };
  26. };
  27. mdio: mdio {
  28. compatible = "virtual,mdio-gpio";
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
  32. <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
  33. pinctrl-0 = <&mdio_pins>;
  34. pinctrl-names = "default";
  35. phy0: ethernet-phy@0 {
  36. reg = <0>;
  37. qca,ar8327-initvals = <
  38. 0x00004 0x7600000 /* PAD0_MODE */
  39. 0x00008 0x1000000 /* PAD5_MODE */
  40. 0x0000c 0x80 /* PAD6_MODE */
  41. 0x000e4 0xaa545 /* MAC_POWER_SEL */
  42. 0x000e0 0xc74164de /* SGMII_CTRL */
  43. 0x0007c 0x4e /* PORT0_STATUS */
  44. 0x00094 0x4e /* PORT6_STATUS */
  45. >;
  46. };
  47. phy1: ethernet-phy@1 {
  48. reg = <1>;
  49. };
  50. };
  51. soc {
  52. rng@1a500000 {
  53. status = "disabled";
  54. };
  55. sound {
  56. compatible = "google,storm-audio";
  57. qcom,model = "ipq806x-storm";
  58. cpu = <&lpass>;
  59. codec = <&max98357a>;
  60. };
  61. lpass: lpass@28100000 {
  62. status = "okay";
  63. pinctrl-names = "default", "idle";
  64. pinctrl-0 = <&mi2s_default>;
  65. pinctrl-1 = <&mi2s_idle>;
  66. };
  67. max98357a: max98357a {
  68. compatible = "maxim,max98357a";
  69. #sound-dai-cells = <1>;
  70. pinctrl-names = "default";
  71. pinctrl-0 = <&sdmode_pins>;
  72. sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
  73. };
  74. };
  75. };
  76. &qcom_pinmux {
  77. rgmii0_pins: rgmii0_pins {
  78. mux {
  79. pins = "gpio2", "gpio66";
  80. drive-strength = <8>;
  81. bias-disable;
  82. };
  83. };
  84. mi2s_pins {
  85. mi2s_default: mi2s_default {
  86. dout {
  87. pins = "gpio32";
  88. function = "mi2s";
  89. drive-strength = <16>;
  90. bias-disable;
  91. };
  92. sync {
  93. pins = "gpio27";
  94. function = "mi2s";
  95. drive-strength = <16>;
  96. bias-disable;
  97. };
  98. clk {
  99. pins = "gpio28";
  100. function = "mi2s";
  101. drive-strength = <16>;
  102. bias-disable;
  103. };
  104. };
  105. mi2s_idle: mi2s_idle {
  106. dout {
  107. pins = "gpio32";
  108. function = "mi2s";
  109. drive-strength = <2>;
  110. bias-pull-down;
  111. };
  112. sync {
  113. pins = "gpio27";
  114. function = "mi2s";
  115. drive-strength = <2>;
  116. bias-pull-down;
  117. };
  118. clk {
  119. pins = "gpio28";
  120. function = "mi2s";
  121. drive-strength = <2>;
  122. bias-pull-down;
  123. };
  124. };
  125. };
  126. mdio_pins: mdio_pins {
  127. mux {
  128. pins = "gpio0", "gpio1";
  129. function = "gpio";
  130. drive-strength = <8>;
  131. bias-disable;
  132. };
  133. rst {
  134. pins = "gpio26";
  135. output-low;
  136. };
  137. };
  138. sdmode_pins: sdmode_pinmux {
  139. pins = "gpio25";
  140. function = "gpio";
  141. drive-strength = <16>;
  142. bias-disable;
  143. };
  144. sdcc1_pins: sdcc1_pinmux {
  145. mux {
  146. pins = "gpio38", "gpio39", "gpio40",
  147. "gpio41", "gpio42", "gpio43",
  148. "gpio44", "gpio45", "gpio46",
  149. "gpio47";
  150. function = "sdc1";
  151. };
  152. cmd {
  153. pins = "gpio45";
  154. drive-strength = <10>;
  155. bias-pull-up;
  156. };
  157. data {
  158. pins = "gpio38", "gpio39", "gpio40",
  159. "gpio41", "gpio43", "gpio44",
  160. "gpio46", "gpio47";
  161. drive-strength = <10>;
  162. bias-pull-up;
  163. };
  164. clk {
  165. pins = "gpio42";
  166. drive-strength = <16>;
  167. bias-pull-down;
  168. };
  169. };
  170. i2c1_pins: i2c1_pinmux {
  171. pins = "gpio53", "gpio54";
  172. function = "gsbi1";
  173. bias-disable;
  174. };
  175. rpm_i2c_pinmux: rpm_i2c_pinmux {
  176. mux {
  177. pins = "gpio12", "gpio13";
  178. function = "gsbi4";
  179. drive-strength = <12>;
  180. bias-disable;
  181. };
  182. };
  183. spi_pins: spi_pins {
  184. mux {
  185. pins = "gpio18", "gpio19", "gpio21";
  186. function = "gsbi5";
  187. bias-pull-down;
  188. /delete-property/ bias-none;
  189. /delete-property/ drive-strength;
  190. };
  191. data {
  192. pins = "gpio18", "gpio19";
  193. drive-strength = <10>;
  194. };
  195. cs {
  196. pins = "gpio20";
  197. drive-strength = <10>;
  198. bias-pull-up;
  199. };
  200. clk {
  201. pins = "gpio21";
  202. drive-strength = <12>;
  203. };
  204. };
  205. fw_pinmux {
  206. wp {
  207. pins = "gpio17";
  208. output-low;
  209. };
  210. recovery {
  211. pins = "gpio16";
  212. bias-none;
  213. };
  214. developer {
  215. pins = "gpio15";
  216. bias-none;
  217. };
  218. };
  219. spi6_pins: spi6_pins {
  220. mux {
  221. pins = "gpio55", "gpio56", "gpio58";
  222. function = "gsbi6";
  223. bias-pull-down;
  224. };
  225. data {
  226. pins = "gpio55", "gpio56";
  227. drive-strength = <10>;
  228. };
  229. cs {
  230. pins = "gpio57";
  231. drive-strength = <10>;
  232. bias-pull-up;
  233. output-high;
  234. };
  235. clk {
  236. pins = "gpio58";
  237. drive-strength = <12>;
  238. };
  239. };
  240. };
  241. &gmac0 {
  242. status = "okay";
  243. phy-mode = "rgmii";
  244. qcom,id = <0>;
  245. phy-handle = <&phy1>;
  246. pinctrl-0 = <&rgmii0_pins>;
  247. pinctrl-names = "default";
  248. fixed-link {
  249. speed = <1000>;
  250. full-duplex;
  251. };
  252. };
  253. &gmac2 {
  254. status = "okay";
  255. phy-mode = "sgmii";
  256. qcom,id = <2>;
  257. phy-handle = <&phy0>;
  258. fixed-link {
  259. speed = <1000>;
  260. full-duplex;
  261. };
  262. };
  263. &gsbi1 {
  264. status = "okay";
  265. qcom,mode = <GSBI_PROT_I2C_UART>;
  266. };
  267. &gsbi1_i2c {
  268. status = "okay";
  269. clock-frequency = <100000>;
  270. pinctrl-0 = <&i2c1_pins>;
  271. pinctrl-names = "default";
  272. tpm@20 {
  273. compatible = "infineon,slb9645tt";
  274. reg = <0x20>;
  275. powered-while-suspended;
  276. };
  277. };
  278. &gsbi4 {
  279. status = "okay";
  280. qcom,mode = <GSBI_PROT_I2C_UART>;
  281. };
  282. &gsbi4_serial {
  283. status = "okay";
  284. };
  285. &gsbi5 {
  286. status = "okay";
  287. qcom,mode = <GSBI_PROT_SPI>;
  288. spi4: spi@1a280000 {
  289. status = "okay";
  290. spi-max-frequency = <50000000>;
  291. pinctrl-0 = <&spi_pins>;
  292. pinctrl-names = "default";
  293. cs-gpios = <&qcom_pinmux 20 0>;
  294. flash: flash@0 {
  295. compatible = "jedec,spi-nor";
  296. spi-max-frequency = <50000000>;
  297. reg = <0>;
  298. };
  299. };
  300. };
  301. &gsbi6 {
  302. status = "okay";
  303. qcom,mode = <GSBI_PROT_SPI>;
  304. };
  305. &gsbi6_spi {
  306. status = "okay";
  307. spi-max-frequency = <25000000>;
  308. pinctrl-0 = <&spi6_pins>;
  309. pinctrl-names = "default";
  310. cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
  311. dmas = <&adm_dma 8 0xb>,
  312. <&adm_dma 7 0x14>;
  313. dma-names = "rx", "tx";
  314. /*
  315. * This "spidev" was included in the manufacturer device tree. I suspect
  316. * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
  317. * no driver or binding for this at the moment.
  318. */
  319. spidev@0 {
  320. compatible = "spidev";
  321. reg = <0>;
  322. spi-max-frequency = <25000000>;
  323. };
  324. };
  325. &pcie0 {
  326. status = "okay";
  327. pcie@0 {
  328. reg = <0 0 0 0 0>;
  329. #interrupt-cells = <1>;
  330. #size-cells = <2>;
  331. #address-cells = <3>;
  332. device_type = "pci";
  333. ath10k@0,0 {
  334. reg = <0 0 0 0 0>;
  335. device_type = "pci";
  336. qcom,ath10k-sa-gpio = <2 3 4 0>;
  337. qcom,ath10k-sa-gpio-func = <5 5 5 0>;
  338. };
  339. };
  340. };
  341. &pcie1 {
  342. status = "okay";
  343. pcie@0 {
  344. reg = <0 0 0 0 0>;
  345. #interrupt-cells = <1>;
  346. #size-cells = <2>;
  347. #address-cells = <3>;
  348. device_type = "pci";
  349. ath10k@0,0 {
  350. reg = <0 0 0 0 0>;
  351. device_type = "pci";
  352. qcom,ath10k-sa-gpio = <2 3 4 0>;
  353. qcom,ath10k-sa-gpio-func = <5 5 5 0>;
  354. };
  355. };
  356. };
  357. &pcie2 {
  358. status = "okay";
  359. pcie@0 {
  360. reg = <0 0 0 0 0>;
  361. #interrupt-cells = <1>;
  362. #size-cells = <2>;
  363. #address-cells = <3>;
  364. device_type = "pci";
  365. ath10k@0,0 {
  366. reg = <0 0 0 0 0>;
  367. device_type = "pci";
  368. };
  369. };
  370. };
  371. &rpm {
  372. pinctrl-0 = <&rpm_i2c_pinmux>;
  373. pinctrl-names = "default";
  374. };
  375. &sdcc1 {
  376. status = "okay";
  377. pinctrl-0 = <&sdcc1_pins>;
  378. pinctrl-names = "default";
  379. /delete-property/ mmc-ddr-1_8v;
  380. };
  381. &tcsr {
  382. compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
  383. qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
  384. };
  385. &hs_phy_0 {
  386. status = "okay";
  387. };
  388. &ss_phy_0 {
  389. status = "okay";
  390. };
  391. &usb3_0 {
  392. status = "okay";
  393. };
  394. &hs_phy_1 {
  395. status = "okay";
  396. };
  397. &ss_phy_1 {
  398. status = "okay";
  399. };
  400. &usb3_1 {
  401. status = "okay";
  402. };