qcom-ipq8065-rt4230w-rev6.dts 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. #include "qcom-ipq8065-smb208.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. model = "Askey RT4230W REV6";
  6. compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
  7. memory@0 {
  8. reg = <0x42000000 0x3e000000>;
  9. device_type = "memory";
  10. };
  11. aliases {
  12. led-boot = &ledctrl3;
  13. led-failsafe = &ledctrl1;
  14. led-running = &ledctrl2;
  15. led-upgrade = &ledctrl3;
  16. };
  17. chosen {
  18. bootargs = "rootfstype=squashfs noinitrd";
  19. };
  20. keys {
  21. compatible = "gpio-keys";
  22. pinctrl-0 = <&button_pins>;
  23. pinctrl-names = "default";
  24. reset {
  25. label = "reset";
  26. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  27. linux,code = <KEY_RESTART>;
  28. };
  29. wps {
  30. label = "wps";
  31. gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  32. linux,code = <KEY_WPS_BUTTON>;
  33. };
  34. };
  35. leds {
  36. compatible = "gpio-leds";
  37. pinctrl-0 = <&led_pins>;
  38. pinctrl-names = "default";
  39. ledctrl1: ledctrl1 {
  40. label = "ledctrl1";
  41. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  42. };
  43. ledctrl2: ledctrl2 {
  44. label = "ledctrl2";
  45. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  46. };
  47. ledctrl3: ledctrl3 {
  48. label = "ledctrl3";
  49. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  50. };
  51. };
  52. };
  53. &qcom_pinmux {
  54. button_pins: button_pins {
  55. mux {
  56. pins = "gpio54", "gpio68";
  57. function = "gpio";
  58. drive-strength = <2>;
  59. bias-pull-up;
  60. };
  61. };
  62. led_pins: led_pins {
  63. mux {
  64. pins = "gpio22", "gpio23", "gpio24";
  65. function = "gpio";
  66. drive-strength = <2>;
  67. bias-pull-down;
  68. };
  69. };
  70. rgmii2_pins: rgmii2-pins {
  71. mux {
  72. pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
  73. "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
  74. function = "rgmii2";
  75. drive-strength = <8>;
  76. bias-disable;
  77. };
  78. tx {
  79. pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
  80. input-disable;
  81. };
  82. };
  83. spi_pins: spi_pins {
  84. cs {
  85. pins = "gpio20";
  86. drive-strength = <12>;
  87. };
  88. };
  89. };
  90. &gsbi5 {
  91. qcom,mode = <GSBI_PROT_SPI>;
  92. status = "okay";
  93. spi@1a280000 {
  94. status = "okay";
  95. pinctrl-0 = <&spi_pins>;
  96. pinctrl-names = "default";
  97. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  98. flash@0 {
  99. compatible = "everspin,mr25h256";
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. spi-max-frequency = <40000000>;
  103. reg = <0>;
  104. };
  105. };
  106. };
  107. &nand {
  108. status = "okay";
  109. nand@0 {
  110. reg = <0>;
  111. compatible = "qcom,nandcs";
  112. nand-ecc-strength = <4>;
  113. nand-bus-width = <8>;
  114. nand-ecc-step-size = <512>;
  115. qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>;
  116. partitions {
  117. compatible = "fixed-partitions";
  118. #address-cells = <1>;
  119. #size-cells = <1>;
  120. partition@0 {
  121. label = "0:SBL1";
  122. reg = <0x0000000 0x0040000>;
  123. read-only;
  124. };
  125. partition@40000 {
  126. label = "0:MIBIB";
  127. reg = <0x0040000 0x0140000>;
  128. read-only;
  129. };
  130. partition@180000 {
  131. label = "0:SBL2";
  132. reg = <0x0180000 0x0140000>;
  133. read-only;
  134. };
  135. partition@2c0000 {
  136. label = "0:SBL3";
  137. reg = <0x02c0000 0x0280000>;
  138. read-only;
  139. };
  140. partition@540000 {
  141. label = "0:DDRCONFIG";
  142. reg = <0x0540000 0x0120000>;
  143. read-only;
  144. };
  145. partition@660000 {
  146. label = "0:SSD";
  147. reg = <0x0660000 0x0120000>;
  148. read-only;
  149. };
  150. partition@780000 {
  151. label = "0:TZ";
  152. reg = <0x0780000 0x0280000>;
  153. read-only;
  154. };
  155. partition@a00000 {
  156. label = "0:RPM";
  157. reg = <0x0a00000 0x0280000>;
  158. read-only;
  159. };
  160. partition@c80000 {
  161. label = "0:APPSBL";
  162. reg = <0x0c80000 0x0500000>;
  163. read-only;
  164. };
  165. partition@1180000 {
  166. label = "0:APPSBLENV";
  167. reg = <0x1180000 0x0080000>;
  168. };
  169. partition@1200000 {
  170. label = "0:ART";
  171. reg = <0x1200000 0x0140000>;
  172. read-only;
  173. compatible = "nvmem-cells";
  174. #address-cells = <1>;
  175. #size-cells = <1>;
  176. macaddr_ART_0: macaddr@0 {
  177. reg = <0x0 0x6>;
  178. };
  179. macaddr_ART_6: macaddr@6 {
  180. reg = <0x6 0x6>;
  181. };
  182. precal_ART_1000: precal@1000 {
  183. reg = <0x1000 0x2f20>;
  184. };
  185. precal_ART_5000: precal@5000 {
  186. reg = <0x5000 0x2f20>;
  187. };
  188. };
  189. partition@1340000 {
  190. label = "0:BOOTCONFIG";
  191. reg = <0x1340000 0x0060000>;
  192. read-only;
  193. };
  194. partition@13a0000 {
  195. label = "0:SBL2_1";
  196. reg = <0x13a0000 0x0140000>;
  197. read-only;
  198. };
  199. partition@14e0000 {
  200. label = "0:SBL3_1";
  201. reg = <0x14e0000 0x0280000>;
  202. read-only;
  203. };
  204. partition@1760000 {
  205. label = "0:DDRCONFIG_1";
  206. reg = <0x1760000 0x0120000>;
  207. read-only;
  208. };
  209. partition@1880000 {
  210. label = "0:SSD_1";
  211. reg = <0x1880000 0x0120000>;
  212. read-only;
  213. };
  214. partition@19a0000 {
  215. label = "0:TZ_1";
  216. reg = <0x19a0000 0x0280000>;
  217. read-only;
  218. };
  219. partition@1c20000 {
  220. label = "0:RPM_1";
  221. reg = <0x1c20000 0x0280000>;
  222. read-only;
  223. };
  224. partition@1ea0000 {
  225. label = "0:BOOTCONFIG1";
  226. reg = <0x1ea0000 0x0060000>;
  227. read-only;
  228. };
  229. partition@1f00000 {
  230. label = "0:APPSBL_1";
  231. reg = <0x1f00000 0x0500000>;
  232. read-only;
  233. };
  234. partition@2400000 {
  235. label = "ubi";
  236. reg = <0x2400000 0x1a000000>;
  237. };
  238. };
  239. };
  240. };
  241. &mdio0 {
  242. status = "okay";
  243. pinctrl-0 = <&mdio0_pins>;
  244. pinctrl-names = "default";
  245. phy0: ethernet-phy@0 {
  246. reg = <0x0>;
  247. qca,ar8327-initvals = <
  248. 0x00004 0x7600000 /* PAD0_MODE */
  249. 0x00008 0x1000000 /* PAD5_MODE */
  250. 0x0000c 0x80 /* PAD6_MODE */
  251. 0x000e4 0xaa545 /* MAC_POWER_SEL */
  252. 0x000e0 0xc74164de /* SGMII_CTRL */
  253. 0x0007c 0x4e /* PORT0_STATUS */
  254. 0x00094 0x4e /* PORT6_STATUS */
  255. 0x00050 0xcf02cf02 /* LED_CTRL_0 */
  256. 0x00054 0xc832c832 /* LED_CTRL_1 */
  257. >;
  258. };
  259. };
  260. &gmac0 {
  261. status = "okay";
  262. phy-mode = "rgmii";
  263. qcom,id = <0>;
  264. nvmem-cells = <&macaddr_ART_0>;
  265. nvmem-cell-names = "mac-address";
  266. pinctrl-0 = <&rgmii2_pins>;
  267. pinctrl-names = "default";
  268. fixed-link {
  269. speed = <1000>;
  270. full-duplex;
  271. };
  272. };
  273. &gmac1 {
  274. status = "okay";
  275. phy-mode = "sgmii";
  276. qcom,id = <1>;
  277. nvmem-cells = <&macaddr_ART_6>;
  278. nvmem-cell-names = "mac-address";
  279. fixed-link {
  280. speed = <1000>;
  281. full-duplex;
  282. };
  283. };
  284. &adm_dma {
  285. status = "okay";
  286. };
  287. &hs_phy_0 {
  288. status = "okay";
  289. };
  290. &ss_phy_0 {
  291. status = "okay";
  292. };
  293. &usb3_0 {
  294. status = "okay";
  295. };
  296. &hs_phy_1 {
  297. status = "okay";
  298. };
  299. &ss_phy_1 {
  300. status = "okay";
  301. };
  302. &usb3_1 {
  303. status = "okay";
  304. };
  305. &pcie0 {
  306. status = "okay";
  307. reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
  308. pinctrl-0 = <&pcie0_pins>;
  309. pinctrl-names = "default";
  310. bridge@0,0 {
  311. reg = <0x00000000 0 0 0 0>;
  312. #address-cells = <3>;
  313. #size-cells = <2>;
  314. ranges;
  315. wifi0: wifi@1,0 {
  316. compatible = "pci168c,0046";
  317. reg = <0x00010000 0 0 0 0>;
  318. nvmem-cells = <&precal_ART_1000>;
  319. nvmem-cell-names = "pre-calibration";
  320. };
  321. };
  322. };
  323. &pcie1 {
  324. status = "okay";
  325. reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
  326. pinctrl-0 = <&pcie1_pins>;
  327. pinctrl-names = "default";
  328. max-link-speed = <1>;
  329. bridge@0,0 {
  330. reg = <0x00000000 0 0 0 0>;
  331. #address-cells = <3>;
  332. #size-cells = <2>;
  333. ranges;
  334. wifi1: wifi@1,0 {
  335. compatible = "pci168c,0046";
  336. reg = <0x00010000 0 0 0 0>;
  337. nvmem-cells = <&precal_ART_5000>;
  338. nvmem-cell-names = "pre-calibration";
  339. };
  340. };
  341. };