ipq8071-eap102.dts 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /* Copyright (c) 2022, Matthew Hagan <[email protected]> */
  3. /dts-v1/;
  4. #include "ipq8074.dtsi"
  5. #include "ipq8074-ac-cpu.dtsi"
  6. #include "ipq8074-ess.dtsi"
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/input/input.h>
  9. / {
  10. model = "Edgecore EAP102";
  11. compatible = "edgecore,eap102", "qcom,ipq8074";
  12. aliases {
  13. serial0 = &blsp1_uart5;
  14. serial1 = &blsp1_uart3;
  15. led-boot = &led_system_green;
  16. led-failsafe = &led_system_green;
  17. led-running = &led_system_green;
  18. led-upgrade = &led_system_green;
  19. /* Aliases as required by u-boot to patch MAC addresses */
  20. ethernet0 = &dp5;
  21. ethernet1 = &dp6;
  22. label-mac-device = &dp5;
  23. };
  24. chosen {
  25. stdout-path = "serial0:115200n8";
  26. bootargs-append = " root=/dev/ubiblock0_1";
  27. };
  28. keys {
  29. compatible = "gpio-keys";
  30. pinctrl-0 = <&button_pins>;
  31. pinctrl-names = "default";
  32. reset {
  33. label = "reset";
  34. gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
  35. linux,code = <KEY_RESTART>;
  36. };
  37. };
  38. leds {
  39. compatible = "gpio-leds";
  40. led_wanpoe {
  41. label = "green:wanpoe";
  42. gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
  43. };
  44. led_wlan2g {
  45. label = "green:wlan2g";
  46. gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
  47. linux,default-trigger = "phy1radio";
  48. };
  49. led_wlan5g {
  50. label = "green:wlan5g";
  51. gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
  52. linux,default-trigger = "phy0radio";
  53. };
  54. led_system_green: led_system {
  55. label = "green:power";
  56. gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
  57. };
  58. };
  59. };
  60. &tlmm {
  61. mdio_pins: mdio-pins {
  62. mdc {
  63. pins = "gpio68";
  64. function = "mdc";
  65. drive-strength = <8>;
  66. bias-pull-up;
  67. };
  68. mdio {
  69. pins = "gpio69";
  70. function = "mdio";
  71. drive-strength = <8>;
  72. bias-pull-up;
  73. };
  74. };
  75. button_pins: button_pins {
  76. reset_button {
  77. pins = "gpio66";
  78. function = "gpio";
  79. drive-strength = <8>;
  80. bias-pull-up;
  81. };
  82. };
  83. };
  84. &blsp1_spi1 {
  85. status = "okay";
  86. flash@0 {
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. reg = <0>;
  90. compatible = "jedec,spi-nor";
  91. spi-max-frequency = <50000000>;
  92. partitions {
  93. compatible = "fixed-partitions";
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. partition@0 {
  97. label = "0:sbl1";
  98. reg = <0x0 0x50000>;
  99. read-only;
  100. };
  101. partition@50000 {
  102. label = "0:mibib";
  103. reg = <0x50000 0x10000>;
  104. read-only;
  105. };
  106. partition@60000 {
  107. label = "0:bootconfig";
  108. reg = <0x60000 0x20000>;
  109. read-only;
  110. };
  111. partition@80000 {
  112. label = "0:bootconfig1";
  113. reg = <0x80000 0x20000>;
  114. read-only;
  115. };
  116. partition@a0000 {
  117. label = "0:qsee";
  118. reg = <0xa0000 0x180000>;
  119. read-only;
  120. };
  121. partition@220000 {
  122. label = "0:qsee_1";
  123. reg = <0x220000 0x180000>;
  124. read-only;
  125. };
  126. partition@3a0000 {
  127. label = "0:devcfg";
  128. reg = <0x3a0000 0x10000>;
  129. read-only;
  130. };
  131. partition@3b0000 {
  132. label = "0:devcfg_1";
  133. reg = <0x3b0000 0x10000>;
  134. read-only;
  135. };
  136. partition@3c0000 {
  137. label = "0:apdp";
  138. reg = <0x3c0000 0x10000>;
  139. read-only;
  140. };
  141. partition@3d0000 {
  142. label = "0:apdp_1";
  143. reg = <0x3d0000 0x10000>;
  144. read-only;
  145. };
  146. partition@3e0000 {
  147. label = "0:rpm";
  148. reg = <0x3e0000 0x40000>;
  149. read-only;
  150. };
  151. partition@420000 {
  152. label = "0:rpm_1";
  153. reg = <0x420000 0x40000>;
  154. read-only;
  155. };
  156. partition@460000 {
  157. label = "0:cdt";
  158. reg = <0x460000 0x10000>;
  159. read-only;
  160. };
  161. partition@470000 {
  162. label = "0:cdt_1";
  163. reg = <0x470000 0x10000>;
  164. read-only;
  165. };
  166. partition@480000 {
  167. label = "0:appsblenv";
  168. reg = <0x480000 0x10000>;
  169. };
  170. partition@490000 {
  171. label = "0:appsbl";
  172. reg = <0x490000 0xc0000>;
  173. read-only;
  174. };
  175. partition@550000 {
  176. label = "0:appsbl_1";
  177. reg = <0x530000 0xc0000>;
  178. read-only;
  179. };
  180. partition@610000 {
  181. label = "0:art";
  182. reg = <0x610000 0x40000>;
  183. read-only;
  184. };
  185. partition@650000 {
  186. label = "0:ethphyfw";
  187. reg = <0x650000 0x80000>;
  188. read-only;
  189. };
  190. partition@6d0000 {
  191. label = "0:product_info";
  192. reg = <0x6d0000 0x80000>;
  193. read-only;
  194. };
  195. partition@750000 {
  196. label = "priv_data1";
  197. reg = <0x750000 0x10000>;
  198. read-only;
  199. };
  200. partition@760000 {
  201. label = "priv_data2";
  202. reg = <0x760000 0x10000>;
  203. read-only;
  204. };
  205. };
  206. };
  207. };
  208. &blsp1_uart3 {
  209. status = "okay";
  210. };
  211. &blsp1_uart5 {
  212. status = "okay";
  213. };
  214. &crypto {
  215. status = "okay";
  216. };
  217. &cryptobam {
  218. status = "okay";
  219. };
  220. &prng {
  221. status = "okay";
  222. };
  223. &qpic_bam {
  224. status = "okay";
  225. };
  226. &qusb_phy_0 {
  227. status = "okay";
  228. };
  229. &ssphy_0 {
  230. status = "okay";
  231. };
  232. &usb_0 {
  233. status = "okay";
  234. };
  235. &qpic_nand {
  236. status = "okay";
  237. nand@0 {
  238. reg = <0>;
  239. nand-ecc-strength = <8>;
  240. nand-ecc-step-size = <512>;
  241. nand-bus-width = <8>;
  242. partitions {
  243. compatible = "fixed-partitions";
  244. #address-cells = <1>;
  245. #size-cells = <1>;
  246. partition@0 {
  247. label = "rootfs1";
  248. reg = <0x0000000 0x3400000>;
  249. };
  250. partition@3400000 {
  251. label = "0:wififw";
  252. reg = <0x3400000 0x800000>;
  253. read-only;
  254. };
  255. partition@3c00000 {
  256. label = "rootfs2";
  257. reg = <0x3c00000 0x3400000>;
  258. };
  259. partition@7000000 {
  260. label = "0:wififw_1";
  261. reg = <0x7000000 0x800000>;
  262. read-only;
  263. };
  264. };
  265. };
  266. };
  267. &mdio {
  268. status = "okay";
  269. pinctrl-0 = <&mdio_pins>;
  270. pinctrl-names = "default";
  271. qca8081_24: ethernet-phy@24 {
  272. compatible = "ethernet-phy-id004d.d101";
  273. reg = <24>;
  274. reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
  275. };
  276. qca8081_28: ethernet-phy@28 {
  277. compatible = "ethernet-phy-id004d.d101";
  278. reg = <28>;
  279. reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
  280. };
  281. };
  282. &switch {
  283. status = "okay";
  284. switch_cpu_bmp = <0x1>; /* cpu port bitmap */
  285. switch_lan_bmp = <0x3e>; /* lan port bitmap */
  286. switch_wan_bmp = <0x40>; /* wan port bitmap */
  287. switch_mac_mode = <0xff>; /* mac mode for uniphy instance0*/
  288. switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
  289. switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/
  290. bm_tick_mode = <0>; /* bm tick mode */
  291. tm_tick_mode = <0>; /* tm tick mode */
  292. qcom,port_phyinfo {
  293. port@4 {
  294. port_id = <5>;
  295. phy_address = <24>;
  296. port_mac_sel = "QGMAC_PORT";
  297. };
  298. port@5 {
  299. port_id = <6>;
  300. phy_address = <28>;
  301. port_mac_sel = "QGMAC_PORT";
  302. };
  303. };
  304. };
  305. &edma {
  306. status = "okay";
  307. };
  308. &dp5 {
  309. status = "okay";
  310. phy-handle = <&qca8081_28>;
  311. label = "wan";
  312. };
  313. &dp6 {
  314. status = "okay";
  315. phy-handle = <&qca8081_24>;
  316. label = "lan";
  317. };
  318. &wifi {
  319. status = "okay";
  320. qcom,ath11k-calibration-variant = "Edgecore-EAP102";
  321. };