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0005-v6.2-arm64-dts-qcom-ipq8074-add-thermal-nodes.patch 3.0 KB

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  1. From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
  2. From: Robert Marko <[email protected]>
  3. Date: Fri, 19 Aug 2022 00:02:45 +0200
  4. Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
  5. IPQ8074 has a tsens v2.3.0 peripheral which monitors
  6. temperatures around the various subsystems on the
  7. die.
  8. So lets add the tsens and thermal zone nodes, passive
  9. CPU cooling will come in later patches after CPU frequency
  10. scaling is supported.
  11. Signed-off-by: Robert Marko <[email protected]>
  12. Signed-off-by: Bjorn Andersson <[email protected]>
  13. Link: https://lore.kernel.org/r/[email protected]
  14. ---
  15. arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
  16. 1 file changed, 96 insertions(+)
  17. --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  18. +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  19. @@ -274,6 +274,16 @@
  20. status = "disabled";
  21. };
  22. + tsens: thermal-sensor@4a9000 {
  23. + compatible = "qcom,ipq8074-tsens";
  24. + reg = <0x4a9000 0x1000>, /* TM */
  25. + <0x4a8000 0x1000>; /* SROT */
  26. + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
  27. + interrupt-names = "combined";
  28. + #qcom,sensors = <16>;
  29. + #thermal-sensor-cells = <1>;
  30. + };
  31. +
  32. cryptobam: dma-controller@704000 {
  33. compatible = "qcom,bam-v1.7.0";
  34. reg = <0x00704000 0x20000>;
  35. @@ -874,4 +884,90 @@
  36. <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  37. <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  38. };
  39. +
  40. + thermal-zones {
  41. + nss-top-thermal {
  42. + polling-delay-passive = <250>;
  43. + polling-delay = <1000>;
  44. +
  45. + thermal-sensors = <&tsens 4>;
  46. + };
  47. +
  48. + nss0-thermal {
  49. + polling-delay-passive = <250>;
  50. + polling-delay = <1000>;
  51. +
  52. + thermal-sensors = <&tsens 5>;
  53. + };
  54. +
  55. + nss1-thermal {
  56. + polling-delay-passive = <250>;
  57. + polling-delay = <1000>;
  58. +
  59. + thermal-sensors = <&tsens 6>;
  60. + };
  61. +
  62. + wcss-phya0-thermal {
  63. + polling-delay-passive = <250>;
  64. + polling-delay = <1000>;
  65. +
  66. + thermal-sensors = <&tsens 7>;
  67. + };
  68. +
  69. + wcss-phya1-thermal {
  70. + polling-delay-passive = <250>;
  71. + polling-delay = <1000>;
  72. +
  73. + thermal-sensors = <&tsens 8>;
  74. + };
  75. +
  76. + cpu0_thermal: cpu0-thermal {
  77. + polling-delay-passive = <250>;
  78. + polling-delay = <1000>;
  79. +
  80. + thermal-sensors = <&tsens 9>;
  81. + };
  82. +
  83. + cpu1_thermal: cpu1-thermal {
  84. + polling-delay-passive = <250>;
  85. + polling-delay = <1000>;
  86. +
  87. + thermal-sensors = <&tsens 10>;
  88. + };
  89. +
  90. + cpu2_thermal: cpu2-thermal {
  91. + polling-delay-passive = <250>;
  92. + polling-delay = <1000>;
  93. +
  94. + thermal-sensors = <&tsens 11>;
  95. + };
  96. +
  97. + cpu3_thermal: cpu3-thermal {
  98. + polling-delay-passive = <250>;
  99. + polling-delay = <1000>;
  100. +
  101. + thermal-sensors = <&tsens 12>;
  102. + };
  103. +
  104. + cluster_thermal: cluster-thermal {
  105. + polling-delay-passive = <250>;
  106. + polling-delay = <1000>;
  107. +
  108. + thermal-sensors = <&tsens 13>;
  109. + };
  110. +
  111. + wcss-phyb0-thermal {
  112. + polling-delay-passive = <250>;
  113. + polling-delay = <1000>;
  114. +
  115. + thermal-sensors = <&tsens 14>;
  116. + };
  117. +
  118. + wcss-phyb1-thermal {
  119. + polling-delay-passive = <250>;
  120. + polling-delay = <1000>;
  121. +
  122. + thermal-sensors = <&tsens 15>;
  123. + };
  124. + };
  125. };