mt7981b-cudy-wr3000-v1.dts 4.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /dts-v1/;
  3. #include "mt7981.dtsi"
  4. / {
  5. model = "Cudy WR3000 v1";
  6. compatible = "cudy,wr3000-v1", "mediatek,mt7981";
  7. aliases {
  8. ethernet0 = &gmac0;
  9. label-mac-device = &lan1;
  10. led-boot = &led_status;
  11. led-failsafe = &led_status;
  12. led-running = &led_status;
  13. led-upgrade = &led_status;
  14. serial0 = &uart0;
  15. };
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. gpio-keys {
  20. compatible = "gpio-keys";
  21. reset {
  22. label = "reset";
  23. linux,code = <KEY_RESTART>;
  24. gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  25. };
  26. wps {
  27. label = "wps";
  28. linux,code = <KEY_WPS_BUTTON>;
  29. gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  30. };
  31. };
  32. leds {
  33. compatible = "gpio-leds";
  34. led_status: led@0 {
  35. label = "blue:status";
  36. gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  37. };
  38. led@1 {
  39. label = "blue:internet";
  40. gpios = <&pio 11 GPIO_ACTIVE_LOW>;
  41. };
  42. led@2 {
  43. label = "blue:wan";
  44. gpios = <&pio 5 GPIO_ACTIVE_LOW>;
  45. };
  46. led@3 {
  47. label = "blue:lan";
  48. gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  49. };
  50. led@4 {
  51. label = "blue:wifi2";
  52. gpios = <&pio 6 GPIO_ACTIVE_LOW>;
  53. linux,default-trigger = "phy0tpt";
  54. };
  55. led@5 {
  56. label = "blue:wifi5";
  57. gpios = <&pio 7 GPIO_ACTIVE_LOW>;
  58. linux,default-trigger = "phy1tpt";
  59. };
  60. };
  61. };
  62. &uart0 {
  63. status = "okay";
  64. };
  65. &watchdog {
  66. status = "okay";
  67. };
  68. &eth {
  69. pinctrl-names = "default";
  70. pinctrl-0 = <&mdio_pins>;
  71. status = "okay";
  72. gmac0: mac@0 {
  73. compatible = "mediatek,eth-mac";
  74. reg = <0>;
  75. phy-mode = "2500base-x";
  76. nvmem-cell-names = "mac-address";
  77. nvmem-cells = <&macaddr_bdinfo_de00>;
  78. fixed-link {
  79. speed = <2500>;
  80. full-duplex;
  81. pause;
  82. };
  83. };
  84. gmac1: mac@1 {
  85. compatible = "mediatek,eth-mac";
  86. reg = <1>;
  87. status = "disabled";
  88. };
  89. };
  90. &mdio_bus {
  91. switch: switch@0 {
  92. compatible = "mediatek,mt7531";
  93. reg = <31>;
  94. reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
  95. };
  96. };
  97. &spi0 {
  98. pinctrl-names = "default";
  99. pinctrl-0 = <&spi0_flash_pins>;
  100. status = "disabled";
  101. };
  102. &spi2 {
  103. pinctrl-names = "default";
  104. pinctrl-0 = <&spi2_flash_pins>;
  105. status = "okay";
  106. flash@0 {
  107. #address-cells = <1>;
  108. #size-cells = <1>;
  109. compatible = "jedec,spi-nor";
  110. reg = <0>;
  111. spi-max-frequency = <25000000>;
  112. spi-tx-buswidth = <4>;
  113. spi-rx-buswidth = <4>;
  114. partitions {
  115. compatible = "fixed-partitions";
  116. #address-cells = <1>;
  117. #size-cells = <1>;
  118. partition@00000 {
  119. label = "BL2";
  120. reg = <0x00000 0x40000>;
  121. read-only;
  122. };
  123. partition@40000 {
  124. label = "u-boot-env";
  125. reg = <0x40000 0x10000>;
  126. read-only;
  127. };
  128. factory: partition@50000 {
  129. label = "Factory";
  130. reg = <0x50000 0x10000>;
  131. read-only;
  132. };
  133. bdinfo: partition@60000 {
  134. label = "bdinfo";
  135. reg = <0x60000 0x10000>;
  136. read-only;
  137. };
  138. partition@70000 {
  139. label = "FIP";
  140. reg = <0x70000 0x80000>;
  141. read-only;
  142. };
  143. partition@f0000 {
  144. compatible = "denx,fit";
  145. label = "firmware";
  146. reg = <0xf0000 0xf10000>;
  147. };
  148. };
  149. };
  150. };
  151. &pio {
  152. spi0_flash_pins: spi0-pins {
  153. mux {
  154. function = "spi";
  155. groups = "spi0", "spi0_wp_hold";
  156. };
  157. };
  158. spi2_flash_pins: spi2-pins {
  159. mux {
  160. function = "spi";
  161. groups = "spi2", "spi2_wp_hold";
  162. };
  163. conf-pu {
  164. pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  165. drive-strength = <8>;
  166. bias-pull-up = <103>;
  167. };
  168. conf-pd {
  169. pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  170. drive-strength = <8>;
  171. bias-pull-down = <103>;
  172. };
  173. };
  174. };
  175. &switch {
  176. ports {
  177. #address-cells = <1>;
  178. #size-cells = <0>;
  179. port@0 {
  180. reg = <0>;
  181. label = "wan";
  182. nvmem-cell-names = "mac-address";
  183. nvmem-cells = <&macaddr_bdinfo_de00>;
  184. mac-address-increment = <1>;
  185. };
  186. lan1: port@1 {
  187. reg = <1>;
  188. label = "lan1";
  189. nvmem-cell-names = "mac-address";
  190. nvmem-cells = <&macaddr_bdinfo_de00>;
  191. };
  192. port@2 {
  193. reg = <2>;
  194. label = "lan2";
  195. nvmem-cell-names = "mac-address";
  196. nvmem-cells = <&macaddr_bdinfo_de00>;
  197. };
  198. port@3 {
  199. reg = <3>;
  200. label = "lan3";
  201. nvmem-cell-names = "mac-address";
  202. nvmem-cells = <&macaddr_bdinfo_de00>;
  203. };
  204. port@6 {
  205. reg = <6>;
  206. label = "cpu";
  207. ethernet = <&gmac0>;
  208. phy-mode = "2500base-x";
  209. fixed-link {
  210. speed = <2500>;
  211. full-duplex;
  212. pause;
  213. };
  214. };
  215. };
  216. };
  217. &wifi {
  218. status = "okay";
  219. mediatek,mtd-eeprom = <&factory 0x0>;
  220. };
  221. &bdinfo {
  222. compatible = "nvmem-cells";
  223. #address-cells = <1>;
  224. #size-cells = <1>;
  225. macaddr_bdinfo_de00: macaddr@de00 {
  226. reg = <0xde00 0x6>;
  227. };
  228. };