0039-soc-mediatek-PMIC-wrap-add-a-slave-specific-struct.patch 10 KB

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  1. From ae593b270b87f9ed6c35dec3ac69dd6bda43c0a0 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Wed, 20 Jan 2016 09:55:08 +0100
  4. Subject: [PATCH 39/81] soc: mediatek: PMIC wrap: add a slave specific struct
  5. This patch adds a new struct pwrap_slv_type that we use to store the slave
  6. specific data. The patch adds 2 new helper functions to access the dew
  7. registers. The slave type is looked up via the wrappers child node.
  8. Signed-off-by: John Crispin <[email protected]>
  9. ---
  10. drivers/soc/mediatek/mtk-pmic-wrap.c | 159 ++++++++++++++++++++++++----------
  11. 1 file changed, 112 insertions(+), 47 deletions(-)
  12. --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
  13. +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
  14. @@ -69,33 +69,54 @@
  15. PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
  16. PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
  17. -/* macro for slave device wrapper registers */
  18. -#define PWRAP_DEW_BASE 0xbc00
  19. -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
  20. -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
  21. -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
  22. -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
  23. -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
  24. -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
  25. -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
  26. -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
  27. -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
  28. -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
  29. -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
  30. -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
  31. -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
  32. -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
  33. -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
  34. -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
  35. -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
  36. -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
  37. -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
  38. -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
  39. -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
  40. -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
  41. -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
  42. -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
  43. -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
  44. +/* defines for slave device wrapper registers */
  45. +enum dew_regs {
  46. + PWRAP_DEW_BASE,
  47. + PWRAP_DEW_DIO_EN,
  48. + PWRAP_DEW_READ_TEST,
  49. + PWRAP_DEW_WRITE_TEST,
  50. + PWRAP_DEW_CRC_EN,
  51. + PWRAP_DEW_CRC_VAL,
  52. + PWRAP_DEW_MON_GRP_SEL,
  53. + PWRAP_DEW_CIPHER_KEY_SEL,
  54. + PWRAP_DEW_CIPHER_IV_SEL,
  55. + PWRAP_DEW_CIPHER_RDY,
  56. + PWRAP_DEW_CIPHER_MODE,
  57. + PWRAP_DEW_CIPHER_SWRST,
  58. +
  59. + /* MT6397 only regs */
  60. + PWRAP_DEW_EVENT_OUT_EN,
  61. + PWRAP_DEW_EVENT_SRC_EN,
  62. + PWRAP_DEW_EVENT_SRC,
  63. + PWRAP_DEW_EVENT_FLAG,
  64. + PWRAP_DEW_MON_FLAG_SEL,
  65. + PWRAP_DEW_EVENT_TEST,
  66. + PWRAP_DEW_CIPHER_LOAD,
  67. + PWRAP_DEW_CIPHER_START,
  68. +};
  69. +
  70. +static const u32 mt6397_regs[] = {
  71. + [PWRAP_DEW_BASE] = 0xbc00,
  72. + [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
  73. + [PWRAP_DEW_DIO_EN] = 0xbc02,
  74. + [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
  75. + [PWRAP_DEW_EVENT_SRC] = 0xbc06,
  76. + [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
  77. + [PWRAP_DEW_READ_TEST] = 0xbc0a,
  78. + [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
  79. + [PWRAP_DEW_CRC_EN] = 0xbc0e,
  80. + [PWRAP_DEW_CRC_VAL] = 0xbc10,
  81. + [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
  82. + [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
  83. + [PWRAP_DEW_EVENT_TEST] = 0xbc16,
  84. + [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
  85. + [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
  86. + [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
  87. + [PWRAP_DEW_CIPHER_START] = 0xbc1e,
  88. + [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
  89. + [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
  90. + [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
  91. +};
  92. enum pwrap_regs {
  93. PWRAP_MUX_SEL,
  94. @@ -349,16 +370,26 @@ static int mt8135_regs[] = {
  95. [PWRAP_DCM_DBC_PRD] = 0x160,
  96. };
  97. +enum pmic_type {
  98. + PMIC_MT6397,
  99. +};
  100. +
  101. enum pwrap_type {
  102. PWRAP_MT8135,
  103. PWRAP_MT8173,
  104. };
  105. +struct pwrap_slv_type {
  106. + const u32 *dew_regs;
  107. + enum pmic_type type;
  108. +};
  109. +
  110. struct pmic_wrapper {
  111. struct device *dev;
  112. void __iomem *base;
  113. struct regmap *regmap;
  114. const struct pmic_wrapper_type *master;
  115. + const struct pwrap_slv_type *slave;
  116. struct clk *clk_spi;
  117. struct clk *clk_wrap;
  118. struct reset_control *rstc;
  119. @@ -544,7 +575,8 @@ static int pwrap_init_sidly(struct pmic_
  120. for (i = 0; i < 4; i++) {
  121. pwrap_writel(wrp, i, PWRAP_SIDLY);
  122. - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
  123. + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
  124. + &rdata);
  125. if (rdata == PWRAP_DEW_READ_TEST_VAL) {
  126. dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
  127. pass |= 1 << i;
  128. @@ -593,7 +625,8 @@ static bool pwrap_is_pmic_cipher_ready(s
  129. u32 rdata;
  130. int ret;
  131. - ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
  132. + ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
  133. + &rdata);
  134. if (ret)
  135. return 0;
  136. @@ -621,12 +654,12 @@ static int pwrap_init_cipher(struct pmic
  137. }
  138. /* Config cipher mode @PMIC */
  139. - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
  140. - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
  141. - pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
  142. - pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
  143. - pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
  144. - pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
  145. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
  146. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
  147. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
  148. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
  149. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1);
  150. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1);
  151. /* wait for cipher data ready@AP */
  152. ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
  153. @@ -643,7 +676,7 @@ static int pwrap_init_cipher(struct pmic
  154. }
  155. /* wait for cipher mode idle */
  156. - pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
  157. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
  158. ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
  159. if (ret) {
  160. dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
  161. @@ -653,9 +686,11 @@ static int pwrap_init_cipher(struct pmic
  162. pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
  163. /* Write Test */
  164. - if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
  165. - pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
  166. - (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
  167. + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
  168. + PWRAP_DEW_WRITE_TEST_VAL) ||
  169. + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
  170. + &rdata) ||
  171. + (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
  172. dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
  173. return -EFAULT;
  174. }
  175. @@ -677,8 +712,10 @@ static int pwrap_mt8135_init_soc_specifi
  176. writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
  177. /* enable PMIC event out and sources */
  178. - if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
  179. - pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
  180. + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
  181. + 0x1) ||
  182. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
  183. + 0xffff)) {
  184. dev_err(wrp->dev, "enable dewrap fail\n");
  185. return -EFAULT;
  186. }
  187. @@ -689,8 +726,10 @@ static int pwrap_mt8135_init_soc_specifi
  188. static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
  189. {
  190. /* PMIC_DEWRAP enables */
  191. - if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
  192. - pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
  193. + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
  194. + 0x1) ||
  195. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
  196. + 0xffff)) {
  197. dev_err(wrp->dev, "enable dewrap fail\n");
  198. return -EFAULT;
  199. }
  200. @@ -734,7 +773,7 @@ static int pwrap_init(struct pmic_wrappe
  201. return ret;
  202. /* Enable dual IO mode */
  203. - pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
  204. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
  205. /* Check IDLE & INIT_DONE in advance */
  206. ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
  207. @@ -746,7 +785,7 @@ static int pwrap_init(struct pmic_wrappe
  208. pwrap_writel(wrp, 1, PWRAP_DIO_EN);
  209. /* Read Test */
  210. - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
  211. + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
  212. if (rdata != PWRAP_DEW_READ_TEST_VAL) {
  213. dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
  214. PWRAP_DEW_READ_TEST_VAL, rdata);
  215. @@ -759,12 +798,13 @@ static int pwrap_init(struct pmic_wrappe
  216. return ret;
  217. /* Signature checking - using CRC */
  218. - if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
  219. + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
  220. return -EFAULT;
  221. pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
  222. pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
  223. - pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
  224. + pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
  225. + PWRAP_SIG_ADR);
  226. pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
  227. if (wrp->master->type == PWRAP_MT8135)
  228. @@ -818,6 +858,21 @@ static const struct regmap_config pwrap_
  229. .max_register = 0xffff,
  230. };
  231. +static const struct pwrap_slv_type pmic_mt6397 = {
  232. + .dew_regs = mt6397_regs,
  233. + .type = PMIC_MT6397,
  234. +};
  235. +
  236. +static const struct of_device_id of_slave_match_tbl[] = {
  237. + {
  238. + .compatible = "mediatek,mt6397",
  239. + .data = &pmic_mt6397,
  240. + }, {
  241. + /* sentinel */
  242. + }
  243. +};
  244. +MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
  245. +
  246. static struct pmic_wrapper_type pwrap_mt8135 = {
  247. .regs = mt8135_regs,
  248. .type = PWRAP_MT8135,
  249. @@ -862,8 +917,17 @@ static int pwrap_probe(struct platform_d
  250. struct device_node *np = pdev->dev.of_node;
  251. const struct of_device_id *of_id =
  252. of_match_device(of_pwrap_match_tbl, &pdev->dev);
  253. + const struct of_device_id *of_slave_id = NULL;
  254. struct resource *res;
  255. + if (pdev->dev.of_node->child)
  256. + of_slave_id = of_match_node(of_slave_match_tbl,
  257. + pdev->dev.of_node->child);
  258. + if (!of_slave_id) {
  259. + dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
  260. + return -EINVAL;
  261. + }
  262. +
  263. wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
  264. if (!wrp)
  265. return -ENOMEM;
  266. @@ -871,6 +935,7 @@ static int pwrap_probe(struct platform_d
  267. platform_set_drvdata(pdev, wrp);
  268. wrp->master = of_id->data;
  269. + wrp->slave = of_slave_id->data;
  270. wrp->dev = &pdev->dev;
  271. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");