747-v5.16-03-net-dsa-qca8k-add-support-for-sgmii-falling-edge.patch 3.8 KB

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  1. From 6c43809bf1bee76c434e365a26546a92a5fbec14 Mon Sep 17 00:00:00 2001
  2. From: Ansuel Smith <[email protected]>
  3. Date: Thu, 14 Oct 2021 00:39:08 +0200
  4. Subject: net: dsa: qca8k: add support for sgmii falling edge
  5. Add support for this in the qca8k driver. Also add support for SGMII
  6. rx/tx clock falling edge. This is only present for pad0, pad5 and
  7. pad6 have these bit reserved from Documentation. Add a comment that this
  8. is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and
  9. setting falling in port0 applies to both configuration with sgmii used
  10. for port0 or port6.
  11. Co-developed-by: Matthew Hagan <[email protected]>
  12. Signed-off-by: Matthew Hagan <[email protected]>
  13. Signed-off-by: Ansuel Smith <[email protected]>
  14. Signed-off-by: David S. Miller <[email protected]>
  15. ---
  16. drivers/net/dsa/qca8k.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++
  17. drivers/net/dsa/qca8k.h | 4 ++++
  18. 2 files changed, 67 insertions(+)
  19. --- a/drivers/net/dsa/qca8k.c
  20. +++ b/drivers/net/dsa/qca8k.c
  21. @@ -978,6 +978,42 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri
  22. }
  23. static int
  24. +qca8k_parse_port_config(struct qca8k_priv *priv)
  25. +{
  26. + struct device_node *port_dn;
  27. + phy_interface_t mode;
  28. + struct dsa_port *dp;
  29. + int port, ret;
  30. +
  31. + /* We have 2 CPU port. Check them */
  32. + for (port = 0; port < QCA8K_NUM_PORTS; port++) {
  33. + /* Skip every other port */
  34. + if (port != 0 && port != 6)
  35. + continue;
  36. +
  37. + dp = dsa_to_port(priv->ds, port);
  38. + port_dn = dp->dn;
  39. +
  40. + if (!of_device_is_available(port_dn))
  41. + continue;
  42. +
  43. + ret = of_get_phy_mode(port_dn, &mode);
  44. + if (ret)
  45. + continue;
  46. +
  47. + if (mode == PHY_INTERFACE_MODE_SGMII) {
  48. + if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
  49. + priv->sgmii_tx_clk_falling_edge = true;
  50. +
  51. + if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
  52. + priv->sgmii_rx_clk_falling_edge = true;
  53. + }
  54. + }
  55. +
  56. + return 0;
  57. +}
  58. +
  59. +static int
  60. qca8k_setup(struct dsa_switch *ds)
  61. {
  62. struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  63. @@ -990,6 +1026,11 @@ qca8k_setup(struct dsa_switch *ds)
  64. return -EINVAL;
  65. }
  66. + /* Parse CPU port config to be later used in phy_link mac_config */
  67. + ret = qca8k_parse_port_config(priv);
  68. + if (ret)
  69. + return ret;
  70. +
  71. mutex_init(&priv->reg_mutex);
  72. /* Start by setting up the register mapping */
  73. @@ -1274,6 +1315,28 @@ qca8k_phylink_mac_config(struct dsa_swit
  74. }
  75. qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
  76. +
  77. + /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
  78. + * falling edge is set writing in the PORT0 PAD reg
  79. + */
  80. + if (priv->switch_id == QCA8K_ID_QCA8327 ||
  81. + priv->switch_id == QCA8K_ID_QCA8337)
  82. + reg = QCA8K_REG_PORT0_PAD_CTRL;
  83. +
  84. + val = 0;
  85. +
  86. + /* SGMII Clock phase configuration */
  87. + if (priv->sgmii_rx_clk_falling_edge)
  88. + val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
  89. +
  90. + if (priv->sgmii_tx_clk_falling_edge)
  91. + val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
  92. +
  93. + if (val)
  94. + ret = qca8k_rmw(priv, reg,
  95. + QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
  96. + QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
  97. + val);
  98. break;
  99. default:
  100. dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
  101. --- a/drivers/net/dsa/qca8k.h
  102. +++ b/drivers/net/dsa/qca8k.h
  103. @@ -35,6 +35,8 @@
  104. #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
  105. #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
  106. #define QCA8K_REG_PORT0_PAD_CTRL 0x004
  107. +#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
  108. +#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18)
  109. #define QCA8K_REG_PORT5_PAD_CTRL 0x008
  110. #define QCA8K_REG_PORT6_PAD_CTRL 0x00c
  111. #define QCA8K_PORT_PAD_RGMII_EN BIT(26)
  112. @@ -260,6 +262,8 @@ struct qca8k_priv {
  113. u8 switch_revision;
  114. u8 rgmii_tx_delay;
  115. u8 rgmii_rx_delay;
  116. + bool sgmii_rx_clk_falling_edge;
  117. + bool sgmii_tx_clk_falling_edge;
  118. bool legacy_phy_port_mapping;
  119. struct regmap *regmap;
  120. struct mii_bus *bus;