qcom-ipq8062-wg2600hp3.dts 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq8062.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. /delete-node/ &nand_pins;
  5. / {
  6. model = "NEC Platforms Aterm WG2600HP3";
  7. compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064";
  8. memory {
  9. device_type = "memory";
  10. reg = <0x42000000 0x1e000000>;
  11. };
  12. aliases {
  13. label-mac-device = &gmac2;
  14. led-boot = &led_power_green;
  15. led-failsafe = &led_power_red;
  16. led-running = &led_power_green;
  17. led-upgrade = &led_power_red;
  18. };
  19. keys {
  20. compatible = "gpio-keys";
  21. pinctrl-0 = <&buttons_pins>;
  22. pinctrl-names = "default";
  23. reset {
  24. label = "reset";
  25. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
  26. linux,code = <KEY_RESTART>;
  27. debounce-interval = <60>;
  28. wakeup-source;
  29. };
  30. wps {
  31. label = "wps";
  32. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
  33. linux,code = <KEY_WPS_BUTTON>;
  34. debounce-interval = <60>;
  35. wakeup-source;
  36. };
  37. mode0 {
  38. label = "mode0";
  39. gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>;
  40. linux,code = <BTN_0>;
  41. linux,input-type = <EV_SW>;
  42. debounce-interval = <60>;
  43. wakeup-source;
  44. };
  45. mode1 {
  46. label = "mode1";
  47. gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>;
  48. linux,code = <BTN_1>;
  49. linux,input-type = <EV_SW>;
  50. debounce-interval = <60>;
  51. wakeup-source;
  52. };
  53. };
  54. leds {
  55. compatible = "gpio-leds";
  56. pinctrl-0 = <&leds_pins>;
  57. pinctrl-names = "default";
  58. led_power_green: power_green {
  59. label = "green:power";
  60. gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
  61. };
  62. led_power_red: power_red {
  63. label = "red:power";
  64. gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>;
  65. };
  66. active_green {
  67. label = "green:active";
  68. gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>;
  69. };
  70. active_red {
  71. label = "red:active";
  72. gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>;
  73. };
  74. wlan2g_green {
  75. label = "green:wlan2g";
  76. gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
  77. linux,default-trigger = "phy1tpt";
  78. };
  79. wlan2g_red {
  80. label = "red:wlan2g";
  81. gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
  82. };
  83. wlan5g_green {
  84. label = "green:wlan5g";
  85. gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
  86. linux,default-trigger = "phy0tpt";
  87. };
  88. wlan5g_red {
  89. label = "red:wlan5g";
  90. gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
  91. };
  92. tv_green {
  93. label = "green:tv";
  94. gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>;
  95. };
  96. tv_red {
  97. label = "red:tv";
  98. gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>;
  99. };
  100. converter_green {
  101. label = "green:converter";
  102. gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>;
  103. };
  104. converter_red {
  105. label = "red:converter";
  106. gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
  107. };
  108. };
  109. };
  110. &qcom_pinmux {
  111. pinctrl-0 = <&akro_pins>;
  112. pinctrl-names = "default";
  113. spi_pins: spi_pins {
  114. mux {
  115. pins = "gpio18", "gpio19", "gpio21";
  116. function = "gsbi5";
  117. bias-pull-down;
  118. };
  119. data {
  120. pins = "gpio18", "gpio19";
  121. drive-strength = <10>;
  122. };
  123. cs {
  124. pins = "gpio20";
  125. drive-strength = <10>;
  126. };
  127. clk {
  128. pins = "gpio21";
  129. drive-strength = <12>;
  130. };
  131. };
  132. buttons_pins: buttons_pins {
  133. mux {
  134. pins = "gpio22", "gpio24", "gpio40",
  135. "gpio41";
  136. function = "gpio";
  137. drive-strength = <2>;
  138. bias-pull-up;
  139. };
  140. };
  141. leds_pins: leds_pins {
  142. mux {
  143. pins = "gpio14", "gpio15", "gpio35",
  144. "gpio36", "gpio38", "gpio42",
  145. "gpio43", "gpio46", "gpio55",
  146. "gpio56", "gpio57", "gpio58";
  147. function = "gpio";
  148. bias-pull-down;
  149. };
  150. akro2 {
  151. pins = "gpio15", "gpio35", "gpio38",
  152. "gpio42", "gpio43", "gpio46",
  153. "gpio55", "gpio56", "gpio57",
  154. "gpio58";
  155. drive-strength = <2>;
  156. };
  157. akro4 {
  158. pins = "gpio14", "gpio36";
  159. drive-strength = <4>;
  160. };
  161. };
  162. /*
  163. * Stock firmware has the following settings, so let's do the same.
  164. * I don't sure why these are required.
  165. */
  166. akro_pins: akro_pinmux {
  167. akro {
  168. pins = "gpio17", "gpio26", "gpio47";
  169. function = "gpio";
  170. drive-strength = <2>;
  171. bias-pull-down;
  172. };
  173. reset {
  174. pins = "gpio45";
  175. function = "gpio";
  176. drive-strength = <2>;
  177. bias-disable;
  178. output-low;
  179. };
  180. gmac0_rgmii {
  181. pins = "gpio25";
  182. function = "gpio";
  183. drive-strength = <8>;
  184. bias-disable;
  185. };
  186. };
  187. };
  188. &gsbi5 {
  189. status = "okay";
  190. qcom,mode = <GSBI_PROT_SPI>;
  191. spi@1a280000 {
  192. status = "okay";
  193. pinctrl-0 = <&spi_pins>;
  194. pinctrl-names = "default";
  195. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  196. flash@0 {
  197. compatible = "jedec,spi-nor";
  198. reg = <0>;
  199. spi-max-frequency = <50000000>;
  200. m25p,fast-read;
  201. partitions {
  202. compatible = "fixed-partitions";
  203. #address-cells = <1>;
  204. #size-cells = <1>;
  205. partition@0 {
  206. label = "SBL1";
  207. reg = <0x0000000 0x0020000>;
  208. read-only;
  209. };
  210. partition@20000 {
  211. label = "MIBIB";
  212. reg = <0x0020000 0x0020000>;
  213. read-only;
  214. };
  215. partition@40000 {
  216. label = "SBL2";
  217. reg = <0x0040000 0x0040000>;
  218. read-only;
  219. };
  220. partition@80000 {
  221. label = "SBL3";
  222. reg = <0x0080000 0x0080000>;
  223. read-only;
  224. };
  225. partition@100000 {
  226. label = "DDRCONFIG";
  227. reg = <0x0100000 0x0010000>;
  228. read-only;
  229. };
  230. partition@110000 {
  231. label = "SSD";
  232. reg = <0x0110000 0x0010000>;
  233. read-only;
  234. };
  235. partition@120000 {
  236. label = "TZ";
  237. reg = <0x0120000 0x0080000>;
  238. read-only;
  239. };
  240. partition@1a0000 {
  241. label = "RPM";
  242. reg = <0x01a0000 0x0080000>;
  243. read-only;
  244. };
  245. partition@220000 {
  246. label = "APPSBL";
  247. reg = <0x0220000 0x0080000>;
  248. read-only;
  249. };
  250. partition@2a0000 {
  251. label = "APPSBLENV";
  252. reg = <0x02a0000 0x0010000>;
  253. read-only;
  254. };
  255. factory: partition@2b0000 {
  256. label = "PRODUCTDATA";
  257. reg = <0x02b0000 0x0030000>;
  258. read-only;
  259. };
  260. partition@2e0000 {
  261. label = "ART";
  262. reg = <0x02e0000 0x0040000>;
  263. read-only;
  264. };
  265. partition@320000 {
  266. label = "TP";
  267. reg = <0x0320000 0x0040000>;
  268. read-only;
  269. };
  270. partition@360000 {
  271. label = "TINY";
  272. reg = <0x0360000 0x0500000>;
  273. read-only;
  274. };
  275. partition@860000 {
  276. compatible = "denx,uimage";
  277. label = "firmware";
  278. reg = <0x0860000 0x17a0000>;
  279. };
  280. };
  281. };
  282. };
  283. };
  284. &adm_dma {
  285. status = "okay";
  286. };
  287. &pcie0 {
  288. status = "okay";
  289. bridge@0,0 {
  290. reg = <0x00000000 0 0 0 0>;
  291. #address-cells = <3>;
  292. #size-cells = <2>;
  293. ranges;
  294. wifi@1,0 {
  295. compatible = "qcom,ath10k";
  296. reg = <0x00010000 0 0 0 0>;
  297. qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
  298. nvmem-cells = <&macaddr_PRODUCTDATA_12>;
  299. nvmem-cell-names = "mac-address";
  300. };
  301. };
  302. };
  303. &pcie1 {
  304. status = "okay";
  305. force_gen1 = <1>;
  306. bridge@0,0 {
  307. reg = <0x00000000 0 0 0 0>;
  308. #address-cells = <3>;
  309. #size-cells = <2>;
  310. ranges;
  311. wifi@1,0 {
  312. compatible = "qcom,ath10k";
  313. reg = <0x00010000 0 0 0 0>;
  314. ieee80211-freq-limit = <2400000 2483000>;
  315. qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
  316. nvmem-cells = <&macaddr_PRODUCTDATA_c>;
  317. nvmem-cell-names = "mac-address";
  318. };
  319. };
  320. };
  321. &mdio0 {
  322. status = "okay";
  323. pinctrl-0 = <&mdio0_pins>;
  324. pinctrl-names = "default";
  325. phy0: ethernet-phy@0 {
  326. reg = <0>;
  327. qca,ar8327-initvals = <
  328. 0x04 0x80080080 /* PAD0_MODE */
  329. 0x0c 0x06000000 /* PAD6_MODE */
  330. 0x10 0x002613a0 /* PWS_REG */
  331. 0x50 0xcc36cc36 /* LED_CTRL0 */
  332. 0x54 0xca36ca36 /* LED_CTRL1 */
  333. 0x58 0xc936c936 /* LED_CTRL2 */
  334. 0x5c 0x03ffff00 /* LED_CTRL3 */
  335. 0x7c 0x0000004e /* PORT0_STATUS */
  336. 0x94 0x0000004e /* PORT6_STATUS */
  337. 0xe0 0xc74164de /* SGMII_CTRL */
  338. 0xe4 0x0006a545 /* MAC_PWR_SEL */
  339. >;
  340. };
  341. };
  342. &gmac1 {
  343. status = "okay";
  344. pinctrl-0 = <&rgmii2_pins>;
  345. pinctrl-names = "default";
  346. phy-mode = "rgmii";
  347. qcom,id = <1>;
  348. mdiobus = <&mdio0>;
  349. nvmem-cells = <&macaddr_factory_0>;
  350. nvmem-cell-names = "mac-address";
  351. fixed-link {
  352. speed = <1000>;
  353. full-duplex;
  354. };
  355. };
  356. &gmac2 {
  357. status = "okay";
  358. phy-mode = "sgmii";
  359. qcom,id = <2>;
  360. mdiobus = <&mdio0>;
  361. nvmem-cells = <&macaddr_factory_6>;
  362. nvmem-cell-names = "mac-address";
  363. fixed-link {
  364. speed = <1000>;
  365. full-duplex;
  366. };
  367. };
  368. &factory {
  369. compatible = "nvmem-cells";
  370. #address-cells = <1>;
  371. #size-cells = <1>;
  372. macaddr_factory_0: macaddr@0 {
  373. reg = <0x0 0x6>;
  374. };
  375. macaddr_factory_6: macaddr@6 {
  376. reg = <0x6 0x6>;
  377. };
  378. macaddr_PRODUCTDATA_c: macaddr@c {
  379. reg = <0xc 0x6>;
  380. };
  381. macaddr_PRODUCTDATA_12: macaddr@12 {
  382. reg = <0x12 0x6>;
  383. };
  384. };