qcom-ipq8064-vr2600v.dts 6.4 KB

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  1. #include "qcom-ipq8064-v2.0.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. / {
  4. model = "TP-Link Archer VR2600v";
  5. compatible = "tplink,vr2600v", "qcom,ipq8064";
  6. memory@0 {
  7. reg = <0x42000000 0x1e000000>;
  8. device_type = "memory";
  9. };
  10. aliases {
  11. mdio-gpio0 = &mdio0;
  12. led-boot = &power;
  13. led-failsafe = &general;
  14. led-running = &power;
  15. led-upgrade = &general;
  16. };
  17. keys {
  18. compatible = "gpio-keys";
  19. pinctrl-0 = <&button_pins>;
  20. pinctrl-names = "default";
  21. wifi {
  22. label = "wifi";
  23. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  24. linux,code = <KEY_RFKILL>;
  25. debounce-interval = <60>;
  26. wakeup-source;
  27. };
  28. reset {
  29. label = "reset";
  30. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
  31. linux,code = <KEY_RESTART>;
  32. debounce-interval = <60>;
  33. wakeup-source;
  34. };
  35. wps {
  36. label = "wps";
  37. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  38. linux,code = <KEY_WPS_BUTTON>;
  39. debounce-interval = <60>;
  40. wakeup-source;
  41. };
  42. dect {
  43. label = "dect";
  44. gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
  45. linux,code = <KEY_PHONE>;
  46. debounce-interval = <60>;
  47. wakeup-source;
  48. };
  49. ledswitch {
  50. label = "ledswitch";
  51. gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  52. linux,code = <KEY_LIGHTS_TOGGLE>;
  53. debounce-interval = <60>;
  54. wakeup-source;
  55. };
  56. };
  57. leds {
  58. compatible = "gpio-leds";
  59. pinctrl-0 = <&led_pins>;
  60. pinctrl-names = "default";
  61. dsl {
  62. label = "white:dsl";
  63. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  64. };
  65. usb {
  66. label = "white:usb";
  67. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  68. };
  69. lan {
  70. label = "white:lan";
  71. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  72. };
  73. wlan2g {
  74. label = "white:wlan2g";
  75. gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
  76. };
  77. wlan5g {
  78. label = "white:wlan5g";
  79. gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
  80. };
  81. power: power {
  82. label = "white:power";
  83. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
  84. default-state = "keep";
  85. };
  86. phone {
  87. label = "white:phone";
  88. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
  89. };
  90. wan {
  91. label = "white:wan";
  92. gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
  93. };
  94. general: general {
  95. label = "white:general";
  96. gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
  97. };
  98. };
  99. };
  100. &qcom_pinmux {
  101. led_pins: led_pins {
  102. mux {
  103. pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17",
  104. "gpio26", "gpio53", "gpio56", "gpio66";
  105. function = "gpio";
  106. drive-strength = <2>;
  107. bias-pull-up;
  108. };
  109. };
  110. button_pins: button_pins {
  111. mux {
  112. pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68";
  113. function = "gpio";
  114. drive-strength = <2>;
  115. bias-pull-up;
  116. };
  117. };
  118. spi_pins: spi_pins {
  119. mux {
  120. pins = "gpio18", "gpio19", "gpio21";
  121. function = "gsbi5";
  122. bias-pull-down;
  123. };
  124. data {
  125. pins = "gpio18", "gpio19";
  126. drive-strength = <10>;
  127. };
  128. cs {
  129. pins = "gpio20";
  130. drive-strength = <10>;
  131. bias-pull-up;
  132. };
  133. clk {
  134. pins = "gpio21";
  135. drive-strength = <12>;
  136. };
  137. };
  138. };
  139. &gsbi5 {
  140. qcom,mode = <GSBI_PROT_SPI>;
  141. status = "okay";
  142. spi4: spi@1a280000 {
  143. status = "okay";
  144. pinctrl-0 = <&spi_pins>;
  145. pinctrl-names = "default";
  146. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  147. W25Q128@0 {
  148. compatible = "jedec,spi-nor";
  149. #address-cells = <1>;
  150. #size-cells = <1>;
  151. spi-max-frequency = <50000000>;
  152. reg = <0>;
  153. SBL1@0 {
  154. label = "SBL1";
  155. reg = <0x0 0x20000>;
  156. read-only;
  157. };
  158. MIBIB@20000 {
  159. label = "MIBIB";
  160. reg = <0x20000 0x20000>;
  161. read-only;
  162. };
  163. SBL2@40000 {
  164. label = "SBL2";
  165. reg = <0x40000 0x40000>;
  166. read-only;
  167. };
  168. SBL3@80000 {
  169. label = "SBL3";
  170. reg = <0x80000 0x80000>;
  171. read-only;
  172. };
  173. DDRCONFIG@100000 {
  174. label = "DDRCONFIG";
  175. reg = <0x100000 0x10000>;
  176. read-only;
  177. };
  178. SSD@110000 {
  179. label = "SSD";
  180. reg = <0x110000 0x10000>;
  181. read-only;
  182. };
  183. TZ@120000 {
  184. label = "TZ";
  185. reg = <0x120000 0x80000>;
  186. read-only;
  187. };
  188. RPM@1a0000 {
  189. label = "RPM";
  190. reg = <0x1a0000 0x80000>;
  191. read-only;
  192. };
  193. APPSBL@220000 {
  194. label = "APPSBL";
  195. reg = <0x220000 0x80000>;
  196. read-only;
  197. };
  198. APPSBLENV@2a0000 {
  199. label = "APPSBLENV";
  200. reg = <0x2a0000 0x40000>;
  201. read-only;
  202. };
  203. OLDART@2e0000 {
  204. label = "OLDART";
  205. reg = <0x2e0000 0x40000>;
  206. read-only;
  207. };
  208. kernel@320000 {
  209. label = "kernel";
  210. reg = <0x320000 0x300000>;
  211. };
  212. rootfs@620000 {
  213. label = "rootfs";
  214. reg = <0x620000 0x960000>;
  215. };
  216. defaultmac: default-mac@0xfaf100 {
  217. label = "default-mac";
  218. reg = <0xfaf100 0x00200>;
  219. read-only;
  220. };
  221. ART@fc0000 {
  222. label = "ART";
  223. reg = <0xfc0000 0x40000>;
  224. read-only;
  225. };
  226. };
  227. };
  228. };
  229. &usb3_0 {
  230. status = "okay";
  231. };
  232. &usb3_1 {
  233. status = "okay";
  234. };
  235. &pcie0 {
  236. status = "okay";
  237. bridge@0,0 {
  238. reg = <0x00000000 0 0 0 0>;
  239. #address-cells = <3>;
  240. #size-cells = <2>;
  241. ranges;
  242. wifi@1,0 {
  243. compatible = "pci168c,0040";
  244. reg = <0x00010000 0 0 0 0>;
  245. nvmem-cells = <&macaddr_defaultmac_0>;
  246. nvmem-cell-names = "mac-address";
  247. mtd-mac-address-increment = <(-1)>;
  248. };
  249. };
  250. };
  251. &pcie1 {
  252. status = "okay";
  253. max-link-speed = <1>;
  254. bridge@0,0 {
  255. reg = <0x00000000 0 0 0 0>;
  256. #address-cells = <3>;
  257. #size-cells = <2>;
  258. ranges;
  259. wifi@1,0 {
  260. compatible = "pci168c,0040";
  261. reg = <0x00010000 0 0 0 0>;
  262. nvmem-cells = <&macaddr_defaultmac_0>;
  263. nvmem-cell-names = "mac-address";
  264. };
  265. };
  266. };
  267. &mdio0 {
  268. status = "okay";
  269. pinctrl-0 = <&mdio0_pins>;
  270. pinctrl-names = "default";
  271. phy0: ethernet-phy@0 {
  272. reg = <0>;
  273. qca,ar8327-initvals = <
  274. 0x00004 0x7600000 /* PAD0_MODE */
  275. 0x00008 0x1000000 /* PAD5_MODE */
  276. 0x0000c 0x80 /* PAD6_MODE */
  277. 0x000e4 0x6a545 /* MAC_POWER_SEL */
  278. 0x000e0 0xc74164de /* SGMII_CTRL */
  279. 0x0007c 0x4e /* PORT0_STATUS */
  280. 0x00094 0x4e /* PORT6_STATUS */
  281. >;
  282. };
  283. phy4: ethernet-phy@4 {
  284. reg = <4>;
  285. };
  286. };
  287. &gmac1 {
  288. status = "okay";
  289. phy-mode = "rgmii";
  290. qcom,id = <1>;
  291. pinctrl-0 = <&rgmii2_pins>;
  292. pinctrl-names = "default";
  293. nvmem-cells = <&macaddr_defaultmac_0>;
  294. nvmem-cell-names = "mac-address";
  295. mac-address-increment = <1>;
  296. fixed-link {
  297. speed = <1000>;
  298. full-duplex;
  299. };
  300. };
  301. &gmac2 {
  302. status = "okay";
  303. phy-mode = "sgmii";
  304. qcom,id = <2>;
  305. nvmem-cells = <&macaddr_defaultmac_0>;
  306. nvmem-cell-names = "mac-address";
  307. fixed-link {
  308. speed = <1000>;
  309. full-duplex;
  310. };
  311. };
  312. &adm_dma {
  313. status = "okay";
  314. };
  315. &defaultmac {
  316. compatible = "nvmem-cells";
  317. #address-cells = <1>;
  318. #size-cells = <1>;
  319. macaddr_defaultmac_0: macaddr@0 {
  320. reg = <0x0 0x6>;
  321. };
  322. };