220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch 20 KB

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  1. From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001
  2. From: AngeloGioacchino Del Regno <[email protected]>
  3. Date: Fri, 20 Jan 2023 10:20:33 +0100
  4. Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with
  5. mtk_clk_register_gates()
  6. Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
  7. introduces a helper function for the sole purpose of propagating a
  8. struct device pointer to the clk API when registering the mtk-gate
  9. clocks to take advantage of Runtime PM when/where needed and where
  10. a power domain is defined in devicetree.
  11. Function mtk_clk_register_gates() then becomes a wrapper around the
  12. new mtk_clk_register_gates_with_dev() function that will simply pass
  13. NULL as struct device: this is essential when registering drivers
  14. with CLK_OF_DECLARE instead of as a platform device, as there will
  15. be no struct device to pass... but we can as well simply have only
  16. one function that always takes such pointer as a param and pass NULL
  17. when unavoidable.
  18. This commit removes the mtk_clk_register_gates() wrapper and renames
  19. mtk_clk_register_gates_with_dev() to the former and all of the calls
  20. to either of the two functions were fixed in all drivers in order to
  21. reflect this change; also, to improve consistency with other kernel
  22. functions, the pointer to struct device was moved as the first param.
  23. Since a lot of MediaTek clock drivers are actually registering as a
  24. platform device, but were still registering the mtk-gate clocks
  25. without passing any struct device to the clock framework, they've
  26. been changed to pass a valid one now, as to make all those platforms
  27. able to use runtime power management where available.
  28. While at it, some much needed indentation changes were also done.
  29. Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
  30. Reviewed-by: Chen-Yu Tsai <[email protected]>
  31. Reviewed-by: Markus Schneider-Pargmann <[email protected]>
  32. Tested-by: Miles Chen <[email protected]>
  33. Link: https://lore.kernel.org/r/[email protected]
  34. Tested-by: Mingming Su <[email protected]>
  35. Signed-off-by: Stephen Boyd <[email protected]>
  36. [[email protected]: dropped parts not relevant for OpenWrt]
  37. ---
  38. drivers/clk/mediatek/clk-gate.c | 23 +++++++---------------
  39. drivers/clk/mediatek/clk-gate.h | 7 +------
  40. drivers/clk/mediatek/clk-mt2701-aud.c | 4 ++--
  41. drivers/clk/mediatek/clk-mt2701-eth.c | 4 ++--
  42. drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +-
  43. drivers/clk/mediatek/clk-mt2701-hif.c | 4 ++--
  44. drivers/clk/mediatek/clk-mt2701-mm.c | 4 ++--
  45. drivers/clk/mediatek/clk-mt2701.c | 12 +++++------
  46. drivers/clk/mediatek/clk-mt2712-mm.c | 4 ++--
  47. drivers/clk/mediatek/clk-mt2712.c | 12 +++++------
  48. drivers/clk/mediatek/clk-mt7622-aud.c | 4 ++--
  49. drivers/clk/mediatek/clk-mt7622-eth.c | 8 ++++----
  50. drivers/clk/mediatek/clk-mt7622-hif.c | 8 ++++----
  51. drivers/clk/mediatek/clk-mt7622.c | 14 ++++++-------
  52. drivers/clk/mediatek/clk-mt7629-eth.c | 7 ++++---
  53. drivers/clk/mediatek/clk-mt7629-hif.c | 8 ++++----
  54. drivers/clk/mediatek/clk-mt7629.c | 10 +++++-----
  55. drivers/clk/mediatek/clk-mt7986-eth.c | 10 +++++-----
  56. drivers/clk/mediatek/clk-mt7986-infracfg.c | 4 ++--
  57. 19 files changed, 68 insertions(+), 81 deletions(-)
  58. --- a/drivers/clk/mediatek/clk-gate.c
  59. +++ b/drivers/clk/mediatek/clk-gate.c
  60. @@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no
  61. };
  62. EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
  63. -static struct clk_hw *mtk_clk_register_gate(const char *name,
  64. +static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
  65. const char *parent_name,
  66. struct regmap *regmap, int set_ofs,
  67. int clr_ofs, int sta_ofs, u8 bit,
  68. const struct clk_ops *ops,
  69. - unsigned long flags, struct device *dev)
  70. + unsigned long flags)
  71. {
  72. struct mtk_clk_gate *cg;
  73. int ret;
  74. @@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru
  75. kfree(cg);
  76. }
  77. -int mtk_clk_register_gates_with_dev(struct device_node *node,
  78. - const struct mtk_gate *clks, int num,
  79. - struct clk_hw_onecell_data *clk_data,
  80. - struct device *dev)
  81. +int mtk_clk_register_gates(struct device *dev, struct device_node *node,
  82. + const struct mtk_gate *clks, int num,
  83. + struct clk_hw_onecell_data *clk_data)
  84. {
  85. int i;
  86. struct clk_hw *hw;
  87. @@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru
  88. continue;
  89. }
  90. - hw = mtk_clk_register_gate(gate->name, gate->parent_name,
  91. + hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
  92. regmap,
  93. gate->regs->set_ofs,
  94. gate->regs->clr_ofs,
  95. gate->regs->sta_ofs,
  96. gate->shift, gate->ops,
  97. - gate->flags, dev);
  98. + gate->flags);
  99. if (IS_ERR(hw)) {
  100. pr_err("Failed to register clk %s: %pe\n", gate->name,
  101. @@ -261,14 +260,6 @@ err:
  102. return PTR_ERR(hw);
  103. }
  104. -EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev);
  105. -
  106. -int mtk_clk_register_gates(struct device_node *node,
  107. - const struct mtk_gate *clks, int num,
  108. - struct clk_hw_onecell_data *clk_data)
  109. -{
  110. - return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
  111. -}
  112. EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
  113. void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
  114. --- a/drivers/clk/mediatek/clk-gate.h
  115. +++ b/drivers/clk/mediatek/clk-gate.h
  116. @@ -50,15 +50,10 @@ struct mtk_gate {
  117. #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
  118. GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
  119. -int mtk_clk_register_gates(struct device_node *node,
  120. +int mtk_clk_register_gates(struct device *dev, struct device_node *node,
  121. const struct mtk_gate *clks, int num,
  122. struct clk_hw_onecell_data *clk_data);
  123. -int mtk_clk_register_gates_with_dev(struct device_node *node,
  124. - const struct mtk_gate *clks, int num,
  125. - struct clk_hw_onecell_data *clk_data,
  126. - struct device *dev);
  127. -
  128. void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
  129. struct clk_hw_onecell_data *clk_data);
  130. --- a/drivers/clk/mediatek/clk-mt2701-aud.c
  131. +++ b/drivers/clk/mediatek/clk-mt2701-aud.c
  132. @@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p
  133. clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
  134. - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
  135. - clk_data);
  136. + mtk_clk_register_gates(&pdev->dev, node, audio_clks,
  137. + ARRAY_SIZE(audio_clks), clk_data);
  138. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  139. if (r) {
  140. --- a/drivers/clk/mediatek/clk-mt2701-eth.c
  141. +++ b/drivers/clk/mediatek/clk-mt2701-eth.c
  142. @@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p
  143. clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
  144. - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
  145. - clk_data);
  146. + mtk_clk_register_gates(&pdev->dev, node, eth_clks,
  147. + ARRAY_SIZE(eth_clks), clk_data);
  148. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  149. if (r)
  150. --- a/drivers/clk/mediatek/clk-mt2701-g3d.c
  151. +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
  152. @@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct
  153. clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
  154. - mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
  155. + mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
  156. clk_data);
  157. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  158. --- a/drivers/clk/mediatek/clk-mt2701-hif.c
  159. +++ b/drivers/clk/mediatek/clk-mt2701-hif.c
  160. @@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p
  161. clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
  162. - mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
  163. - clk_data);
  164. + mtk_clk_register_gates(&pdev->dev, node, hif_clks,
  165. + ARRAY_SIZE(hif_clks), clk_data);
  166. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  167. if (r) {
  168. --- a/drivers/clk/mediatek/clk-mt2701-mm.c
  169. +++ b/drivers/clk/mediatek/clk-mt2701-mm.c
  170. @@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl
  171. clk_data = mtk_alloc_clk_data(CLK_MM_NR);
  172. - mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
  173. - clk_data);
  174. + mtk_clk_register_gates(&pdev->dev, node, mm_clks,
  175. + ARRAY_SIZE(mm_clks), clk_data);
  176. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  177. if (r)
  178. --- a/drivers/clk/mediatek/clk-mt2701.c
  179. +++ b/drivers/clk/mediatek/clk-mt2701.c
  180. @@ -685,8 +685,8 @@ static int mtk_topckgen_init(struct plat
  181. mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
  182. base, &mt2701_clk_lock, clk_data);
  183. - mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
  184. - clk_data);
  185. + mtk_clk_register_gates(&pdev->dev, node, top_clks,
  186. + ARRAY_SIZE(top_clks), clk_data);
  187. return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  188. }
  189. @@ -789,8 +789,8 @@ static int mtk_infrasys_init(struct plat
  190. }
  191. }
  192. - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  193. - infra_clk_data);
  194. + mtk_clk_register_gates(&pdev->dev, node, infra_clks,
  195. + ARRAY_SIZE(infra_clks), infra_clk_data);
  196. mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
  197. infra_clk_data);
  198. @@ -902,8 +902,8 @@ static int mtk_pericfg_init(struct platf
  199. if (!clk_data)
  200. return -ENOMEM;
  201. - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
  202. - clk_data);
  203. + mtk_clk_register_gates(&pdev->dev, node, peri_clks,
  204. + ARRAY_SIZE(peri_clks), clk_data);
  205. mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
  206. &mt2701_clk_lock, clk_data);
  207. --- a/drivers/clk/mediatek/clk-mt2712-mm.c
  208. +++ b/drivers/clk/mediatek/clk-mt2712-mm.c
  209. @@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl
  210. clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
  211. - mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
  212. - clk_data);
  213. + mtk_clk_register_gates(&pdev->dev, node, mm_clks,
  214. + ARRAY_SIZE(mm_clks), clk_data);
  215. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  216. --- a/drivers/clk/mediatek/clk-mt2712.c
  217. +++ b/drivers/clk/mediatek/clk-mt2712.c
  218. @@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p
  219. &mt2712_clk_lock, top_clk_data);
  220. mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
  221. &mt2712_clk_lock, top_clk_data);
  222. - mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
  223. - top_clk_data);
  224. + mtk_clk_register_gates(&pdev->dev, node, top_clks,
  225. + ARRAY_SIZE(top_clks), top_clk_data);
  226. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
  227. @@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct
  228. clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
  229. - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  230. - clk_data);
  231. + mtk_clk_register_gates(&pdev->dev, node, infra_clks,
  232. + ARRAY_SIZE(infra_clks), clk_data);
  233. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  234. @@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct
  235. clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
  236. - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
  237. - clk_data);
  238. + mtk_clk_register_gates(&pdev->dev, node, peri_clks,
  239. + ARRAY_SIZE(peri_clks), clk_data);
  240. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  241. --- a/drivers/clk/mediatek/clk-mt7622-aud.c
  242. +++ b/drivers/clk/mediatek/clk-mt7622-aud.c
  243. @@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru
  244. clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
  245. - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
  246. - clk_data);
  247. + mtk_clk_register_gates(&pdev->dev, node, audio_clks,
  248. + ARRAY_SIZE(audio_clks), clk_data);
  249. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  250. if (r) {
  251. --- a/drivers/clk/mediatek/clk-mt7622-eth.c
  252. +++ b/drivers/clk/mediatek/clk-mt7622-eth.c
  253. @@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct
  254. clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
  255. - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
  256. - clk_data);
  257. + mtk_clk_register_gates(&pdev->dev, node, eth_clks,
  258. + ARRAY_SIZE(eth_clks), clk_data);
  259. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  260. if (r)
  261. @@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru
  262. clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
  263. - mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
  264. - clk_data);
  265. + mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
  266. + ARRAY_SIZE(sgmii_clks), clk_data);
  267. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  268. if (r)
  269. --- a/drivers/clk/mediatek/clk-mt7622-hif.c
  270. +++ b/drivers/clk/mediatek/clk-mt7622-hif.c
  271. @@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru
  272. clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
  273. - mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
  274. - clk_data);
  275. + mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
  276. + ARRAY_SIZE(ssusb_clks), clk_data);
  277. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  278. if (r)
  279. @@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc
  280. clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
  281. - mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
  282. - clk_data);
  283. + mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
  284. + ARRAY_SIZE(pcie_clks), clk_data);
  285. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  286. if (r)
  287. --- a/drivers/clk/mediatek/clk-mt7622.c
  288. +++ b/drivers/clk/mediatek/clk-mt7622.c
  289. @@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat
  290. mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
  291. base, &mt7622_clk_lock, clk_data);
  292. - mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
  293. - clk_data);
  294. + mtk_clk_register_gates(&pdev->dev, node, top_clks,
  295. + ARRAY_SIZE(top_clks), clk_data);
  296. return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  297. }
  298. @@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat
  299. clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
  300. - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  301. - clk_data);
  302. + mtk_clk_register_gates(&pdev->dev, node, infra_clks,
  303. + ARRAY_SIZE(infra_clks), clk_data);
  304. mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
  305. clk_data);
  306. @@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl
  307. mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
  308. clk_data);
  309. - mtk_clk_register_gates(node, apmixed_clks,
  310. + mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
  311. ARRAY_SIZE(apmixed_clks), clk_data);
  312. return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  313. @@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf
  314. clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
  315. - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
  316. - clk_data);
  317. + mtk_clk_register_gates(&pdev->dev, node, peri_clks,
  318. + ARRAY_SIZE(peri_clks), clk_data);
  319. mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
  320. &mt7622_clk_lock, clk_data);
  321. --- a/drivers/clk/mediatek/clk-mt7629-eth.c
  322. +++ b/drivers/clk/mediatek/clk-mt7629-eth.c
  323. @@ -82,7 +82,8 @@ static int clk_mt7629_ethsys_init(struct
  324. if (!clk_data)
  325. return -ENOMEM;
  326. - mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
  327. + mtk_clk_register_gates(&pdev->dev, node, eth_clks,
  328. + CLK_ETH_NR_CLK, clk_data);
  329. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  330. if (r)
  331. @@ -106,8 +107,8 @@ static int clk_mt7629_sgmiisys_init(stru
  332. if (!clk_data)
  333. return -ENOMEM;
  334. - mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
  335. - clk_data);
  336. + mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
  337. + CLK_SGMII_NR_CLK, clk_data);
  338. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  339. if (r)
  340. --- a/drivers/clk/mediatek/clk-mt7629-hif.c
  341. +++ b/drivers/clk/mediatek/clk-mt7629-hif.c
  342. @@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru
  343. clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
  344. - mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
  345. - clk_data);
  346. + mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
  347. + ARRAY_SIZE(ssusb_clks), clk_data);
  348. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  349. if (r)
  350. @@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc
  351. clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
  352. - mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
  353. - clk_data);
  354. + mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
  355. + ARRAY_SIZE(pcie_clks), clk_data);
  356. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  357. if (r)
  358. --- a/drivers/clk/mediatek/clk-mt7629.c
  359. +++ b/drivers/clk/mediatek/clk-mt7629.c
  360. @@ -585,8 +585,8 @@ static int mtk_infrasys_init(struct plat
  361. if (!clk_data)
  362. return -ENOMEM;
  363. - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  364. - clk_data);
  365. + mtk_clk_register_gates(&pdev->dev, node, infra_clks,
  366. + ARRAY_SIZE(infra_clks), clk_data);
  367. mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
  368. clk_data);
  369. @@ -610,8 +610,8 @@ static int mtk_pericfg_init(struct platf
  370. if (!clk_data)
  371. return -ENOMEM;
  372. - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
  373. - clk_data);
  374. + mtk_clk_register_gates(&pdev->dev, node, peri_clks,
  375. + ARRAY_SIZE(peri_clks), clk_data);
  376. mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
  377. &mt7629_clk_lock, clk_data);
  378. @@ -637,7 +637,7 @@ static int mtk_apmixedsys_init(struct pl
  379. mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
  380. clk_data);
  381. - mtk_clk_register_gates(node, apmixed_clks,
  382. + mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
  383. ARRAY_SIZE(apmixed_clks), clk_data);
  384. clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
  385. --- a/drivers/clk/mediatek/clk-mt7986-eth.c
  386. +++ b/drivers/clk/mediatek/clk-mt7986-eth.c
  387. @@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s
  388. clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
  389. - mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
  390. - clk_data);
  391. + mtk_clk_register_gates(NULL, node, sgmii0_clks,
  392. + ARRAY_SIZE(sgmii0_clks), clk_data);
  393. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  394. if (r)
  395. @@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s
  396. clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
  397. - mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
  398. - clk_data);
  399. + mtk_clk_register_gates(NULL, node, sgmii1_clks,
  400. + ARRAY_SIZE(sgmii1_clks), clk_data);
  401. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  402. @@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc
  403. clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
  404. - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
  405. + mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
  406. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  407. --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
  408. +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
  409. @@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str
  410. mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
  411. mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
  412. &mt7986_clk_lock, clk_data);
  413. - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  414. - clk_data);
  415. + mtk_clk_register_gates(&pdev->dev, node, infra_clks,
  416. + ARRAY_SIZE(infra_clks), clk_data);
  417. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  418. if (r) {
  419. --- a/drivers/clk/mediatek/clk-mtk.c
  420. +++ b/drivers/clk/mediatek/clk-mtk.c
  421. @@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform
  422. if (!clk_data)
  423. return -ENOMEM;
  424. - r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks,
  425. - clk_data, &pdev->dev);
  426. + r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
  427. + clk_data);
  428. if (r)
  429. goto free_data;