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- From: qizhong cheng <[email protected]>
- Date: Mon, 27 Dec 2021 21:31:10 +0800
- Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
- stabilize
- MIME-Version: 1.0
- Content-Type: text/plain; charset=UTF-8
- Content-Transfer-Encoding: 8bit
- Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
- 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
- be delayed 100ms (TPVPERL) for the power and clock to become stable.
- Link: https://lore.kernel.org/r/[email protected]
- Signed-off-by: qizhong cheng <[email protected]>
- Signed-off-by: Lorenzo Pieralisi <[email protected]>
- Acked-by: Pali Rohár <[email protected]>
- ---
- --- a/drivers/pci/controller/pcie-mediatek.c
- +++ b/drivers/pci/controller/pcie-mediatek.c
- @@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru
- */
- msleep(100);
-
- + /*
- + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
- + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
- + * be delayed 100ms (TPVPERL) for the power and clock to become stable.
- + */
- + msleep(100);
- +
- /* De-assert PHY, PE, PIPE, MAC and configuration reset */
- val = readl(port->base + PCIE_RST_CTRL);
- val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
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