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- --- a/drivers/net/wireless/b43/phy_n.c
- +++ b/drivers/net/wireless/b43/phy_n.c
- @@ -5165,7 +5165,8 @@ static void b43_nphy_pmu_spur_avoid(stru
- #endif
- #ifdef CONFIG_B43_SSB
- case B43_BUS_SSB:
- - /* FIXME */
- + ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
- + avoid);
- break;
- #endif
- }
- --- a/drivers/ssb/driver_chipcommon_pmu.c
- +++ b/drivers/ssb/driver_chipcommon_pmu.c
- @@ -675,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_
- return 0;
- }
- }
- +
- +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
- +{
- + u32 pmu_ctl = 0;
- +
- + switch (cc->dev->bus->chip_id) {
- + case 0x4322:
- + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
- + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
- + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
- + if (spuravoid == 1)
- + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
- + else
- + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
- + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
- + break;
- + case 43222:
- + /* TODO: BCM43222 requires updating PLLs too */
- + return;
- + default:
- + ssb_printk(KERN_ERR PFX
- + "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
- + cc->dev->bus->chip_id);
- + return;
- + }
- +
- + chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
- +}
- +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
- --- a/drivers/ssb/pci.c
- +++ b/drivers/ssb/pci.c
- @@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_
- return (s8)gain;
- }
-
- +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
- +{
- + SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
- + SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
- + SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
- + SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
- + SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
- + SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
- + SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
- + SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
- + SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
- + SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
- + SSB_SPROM2_MAXP_A_LO_SHIFT);
- +}
- +
- static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
- {
- int i;
- @@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss
- SSB_SPROM1_ITSSI_A_SHIFT);
- SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
- SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
- - if (out->revision >= 2)
- - SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
- +
- SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
- SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
-
- @@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss
- out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
- SSB_SPROM1_AGAIN_A,
- SSB_SPROM1_AGAIN_A_SHIFT);
- + if (out->revision >= 2)
- + sprom_extract_r23(out, in);
- }
-
- /* Revs 4 5 and 8 have partially shared layout */
- --- a/include/linux/ssb/ssb_driver_chipcommon.h
- +++ b/include/linux/ssb/ssb_driver_chipcommon.h
- @@ -219,6 +219,7 @@
- #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
- #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
- #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
- +#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
- #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
- #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
- #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
- @@ -667,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
- void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
- enum ssb_pmu_ldo_volt_id id, u32 voltage);
- void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
- +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
-
- #endif /* LINUX_SSB_CHIPCO_H_ */
- --- a/include/linux/ssb/ssb_regs.h
- +++ b/include/linux/ssb/ssb_regs.h
- @@ -289,11 +289,11 @@
- #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
- #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
- #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
- -#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
- -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
- -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
- -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
- -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
- +#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
- +#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
- +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
- +#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
- +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
- #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
- #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
- #define SSB_SPROM4_AGAIN0_SHIFT 0
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