100-board_support.patch 3.0 KB

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  1. Index: linux-2.6.24.7/arch/mips/Kconfig
  2. ===================================================================
  3. --- linux-2.6.24.7.orig/arch/mips/Kconfig
  4. +++ linux-2.6.24.7/arch/mips/Kconfig
  5. @@ -16,6 +16,24 @@ choice
  6. prompt "System type"
  7. default SGI_IP22
  8. +config AR7
  9. + bool "Texas Instruments AR7"
  10. + select BOOT_ELF32
  11. + select DMA_NONCOHERENT
  12. + select CEVT_R4K
  13. + select CSRC_R4K
  14. + select IRQ_CPU
  15. + select NO_EXCEPT_FILL
  16. + select SWAP_IO_SPACE
  17. + select SYS_HAS_CPU_MIPS32_R1
  18. + select SYS_HAS_EARLY_PRINTK
  19. + select SYS_SUPPORTS_32BIT_KERNEL
  20. + select SYS_SUPPORTS_KGDB
  21. + select SYS_SUPPORTS_LITTLE_ENDIAN
  22. + select SYS_SUPPORTS_BIG_ENDIAN
  23. + select GENERIC_GPIO
  24. + select GENERIC_HARDIRQS_NO__DO_IRQ
  25. +
  26. config MACH_ALCHEMY
  27. bool "Alchemy processor based machines"
  28. Index: linux-2.6.24.7/arch/mips/kernel/traps.c
  29. ===================================================================
  30. --- linux-2.6.24.7.orig/arch/mips/kernel/traps.c
  31. +++ linux-2.6.24.7/arch/mips/kernel/traps.c
  32. @@ -1093,9 +1093,22 @@ void *set_except_vector(int n, void *add
  33. exception_handlers[n] = handler;
  34. if (n == 0 && cpu_has_divec) {
  35. - *(u32 *)(ebase + 0x200) = 0x08000000 |
  36. - (0x03ffffff & (handler >> 2));
  37. - flush_icache_range(ebase + 0x200, ebase + 0x204);
  38. + if ((handler ^ (ebase + 4)) & 0xfc000000) {
  39. + /* lui k0, 0x0000 */
  40. + *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
  41. + /* ori k0, 0x0000 */
  42. + *(u32 *)(ebase + 0x204) =
  43. + 0x375a0000 | (handler & 0xffff);
  44. + /* jr k0 */
  45. + *(u32 *)(ebase + 0x208) = 0x03400008;
  46. + /* nop */
  47. + *(u32 *)(ebase + 0x20C) = 0x00000000;
  48. + flush_icache_range(ebase + 0x200, ebase + 0x210);
  49. + } else {
  50. + *(u32 *)(ebase + 0x200) =
  51. + 0x08000000 | (0x03ffffff & (handler >> 2));
  52. + flush_icache_range(ebase + 0x200, ebase + 0x204);
  53. + }
  54. }
  55. return (void *)old_handler;
  56. }
  57. Index: linux-2.6.24.7/arch/mips/Makefile
  58. ===================================================================
  59. --- linux-2.6.24.7.orig/arch/mips/Makefile
  60. +++ linux-2.6.24.7/arch/mips/Makefile
  61. @@ -159,6 +159,13 @@ libs-$(CONFIG_SIBYTE_CFE) += arch/mips/s
  62. #
  63. #
  64. +# Texas Instruments AR7
  65. +#
  66. +core-$(CONFIG_AR7) += arch/mips/ar7/
  67. +cflags-$(CONFIG_AR7) += -Iinclude/asm-mips/ar7
  68. +load-$(CONFIG_AR7) += 0xffffffff94100000
  69. +
  70. +#
  71. # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
  72. #
  73. core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
  74. Index: linux-2.6.24.7/include/asm-mips/page.h
  75. ===================================================================
  76. --- linux-2.6.24.7.orig/include/asm-mips/page.h
  77. +++ linux-2.6.24.7/include/asm-mips/page.h
  78. @@ -184,8 +184,10 @@ typedef struct { unsigned long pgprot; }
  79. #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
  80. VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
  81. -#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
  82. -#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
  83. +#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \
  84. + PHYS_OFFSET)
  85. +#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \
  86. + PHYS_OFFSET)
  87. #include <asm-generic/memory_model.h>
  88. #include <asm-generic/page.h>