750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch 4.3 KB

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  1. From 199e7d5a7f03dd377f3a7a458360dbedd71d50ba Mon Sep 17 00:00:00 2001
  2. From: Lorenzo Bianconi <[email protected]>
  3. Date: Thu, 27 Jul 2023 09:07:28 +0200
  4. Subject: [PATCH 107/250] net: ethernet: mtk_eth_soc: enable nft hw
  5. flowtable_offload for MT7988 SoC
  6. Enable hw Packet Process Engine (PPE) for MT7988 SoC.
  7. Tested-by: Daniel Golle <[email protected]>
  8. Signed-off-by: Lorenzo Bianconi <[email protected]>
  9. Link: https://lore.kernel.org/r/5e86341b0220a49620dadc02d77970de5ded9efc.1690441576.git.lorenzo@kernel.org
  10. Signed-off-by: Jakub Kicinski <[email protected]>
  11. ---
  12. drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 +++
  13. drivers/net/ethernet/mediatek/mtk_ppe.c | 19 +++++++++++++++----
  14. drivers/net/ethernet/mediatek/mtk_ppe.h | 19 ++++++++++++++++++-
  15. 3 files changed, 36 insertions(+), 5 deletions(-)
  16. --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  17. +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  18. @@ -4974,6 +4974,9 @@ static const struct mtk_soc_data mt7988_
  19. .required_clks = MT7988_CLKS_BITMAP,
  20. .required_pctl = false,
  21. .version = 3,
  22. + .offload_version = 2,
  23. + .hash_offset = 4,
  24. + .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
  25. .txrx = {
  26. .txd_size = sizeof(struct mtk_tx_dma_v2),
  27. .rxd_size = sizeof(struct mtk_rx_dma_v2),
  28. --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
  29. +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
  30. @@ -422,13 +422,22 @@ int mtk_foe_entry_set_wdma(struct mtk_et
  31. struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
  32. u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
  33. - if (mtk_is_netsys_v2_or_greater(eth)) {
  34. + switch (eth->soc->version) {
  35. + case 3:
  36. + *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
  37. + *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
  38. + MTK_FOE_IB2_WDMA_WINFO_V2;
  39. + l2->w3info = FIELD_PREP(MTK_FOE_WINFO_WCID_V3, wcid) |
  40. + FIELD_PREP(MTK_FOE_WINFO_BSS_V3, bss);
  41. + break;
  42. + case 2:
  43. *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
  44. *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
  45. MTK_FOE_IB2_WDMA_WINFO_V2;
  46. l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) |
  47. FIELD_PREP(MTK_FOE_WINFO_BSS, bss);
  48. - } else {
  49. + break;
  50. + default:
  51. *ib2 &= ~MTK_FOE_IB2_PORT_MG;
  52. *ib2 |= MTK_FOE_IB2_WDMA_WINFO;
  53. if (wdma_idx)
  54. @@ -436,6 +445,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et
  55. l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) |
  56. FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) |
  57. FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq);
  58. + break;
  59. }
  60. return 0;
  61. @@ -956,8 +966,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
  62. mtk_ppe_init_foe_table(ppe);
  63. ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
  64. - val = MTK_PPE_TB_CFG_ENTRY_80B |
  65. - MTK_PPE_TB_CFG_AGE_NON_L4 |
  66. + val = MTK_PPE_TB_CFG_AGE_NON_L4 |
  67. MTK_PPE_TB_CFG_AGE_UNBIND |
  68. MTK_PPE_TB_CFG_AGE_TCP |
  69. MTK_PPE_TB_CFG_AGE_UDP |
  70. @@ -973,6 +982,8 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
  71. MTK_PPE_ENTRIES_SHIFT);
  72. if (mtk_is_netsys_v2_or_greater(ppe->eth))
  73. val |= MTK_PPE_TB_CFG_INFO_SEL;
  74. + if (!mtk_is_netsys_v3_or_greater(ppe->eth))
  75. + val |= MTK_PPE_TB_CFG_ENTRY_80B;
  76. ppe_w32(ppe, MTK_PPE_TB_CFG, val);
  77. ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,
  78. --- a/drivers/net/ethernet/mediatek/mtk_ppe.h
  79. +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
  80. @@ -85,6 +85,17 @@ enum {
  81. #define MTK_FOE_WINFO_BSS GENMASK(5, 0)
  82. #define MTK_FOE_WINFO_WCID GENMASK(15, 6)
  83. +#define MTK_FOE_WINFO_BSS_V3 GENMASK(23, 16)
  84. +#define MTK_FOE_WINFO_WCID_V3 GENMASK(15, 0)
  85. +
  86. +#define MTK_FOE_WINFO_PAO_USR_INFO GENMASK(15, 0)
  87. +#define MTK_FOE_WINFO_PAO_TID GENMASK(19, 16)
  88. +#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE BIT(20)
  89. +#define MTK_FOE_WINFO_PAO_IS_PRIOR BIT(21)
  90. +#define MTK_FOE_WINFO_PAO_IS_SP BIT(22)
  91. +#define MTK_FOE_WINFO_PAO_HF BIT(23)
  92. +#define MTK_FOE_WINFO_PAO_AMSDU_EN BIT(24)
  93. +
  94. enum {
  95. MTK_FOE_STATE_INVALID,
  96. MTK_FOE_STATE_UNBIND,
  97. @@ -106,8 +117,13 @@ struct mtk_foe_mac_info {
  98. u16 pppoe_id;
  99. u16 src_mac_lo;
  100. + /* netsys_v2 */
  101. u16 minfo;
  102. u16 winfo;
  103. +
  104. + /* netsys_v3 */
  105. + u32 w3info;
  106. + u32 wpao;
  107. };
  108. /* software-only entry type */
  109. @@ -218,6 +234,7 @@ struct mtk_foe_ipv6_6rd {
  110. #define MTK_FOE_ENTRY_V1_SIZE 80
  111. #define MTK_FOE_ENTRY_V2_SIZE 96
  112. +#define MTK_FOE_ENTRY_V3_SIZE 128
  113. struct mtk_foe_entry {
  114. u32 ib1;
  115. @@ -228,7 +245,7 @@ struct mtk_foe_entry {
  116. struct mtk_foe_ipv4_dslite dslite;
  117. struct mtk_foe_ipv6 ipv6;
  118. struct mtk_foe_ipv6_6rd ipv6_6rd;
  119. - u32 data[23];
  120. + u32 data[31];
  121. };
  122. };