050-v5.16-00-MIPS-uasm-Enable-muhu-opcode-for-MIPS-R6.patch 2.4 KB

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  1. From: Johan Almbladh <[email protected]>
  2. Date: Tue, 5 Oct 2021 18:54:02 +0200
  3. Subject: [PATCH] MIPS: uasm: Enable muhu opcode for MIPS R6
  4. Enable the 'muhu' instruction, complementing the existing 'mulu', needed
  5. to implement a MIPS32 BPF JIT.
  6. Also fix a typo in the existing definition of 'dmulu'.
  7. Signed-off-by: Tony Ambardar <[email protected]>
  8. This patch is a dependency for my 32-bit MIPS eBPF JIT.
  9. Signed-off-by: Johan Almbladh <[email protected]>
  10. ---
  11. --- a/arch/mips/include/asm/uasm.h
  12. +++ b/arch/mips/include/asm/uasm.h
  13. @@ -145,6 +145,7 @@ Ip_u1(_mtlo);
  14. Ip_u3u1u2(_mul);
  15. Ip_u1u2(_multu);
  16. Ip_u3u1u2(_mulu);
  17. +Ip_u3u1u2(_muhu);
  18. Ip_u3u1u2(_nor);
  19. Ip_u3u1u2(_or);
  20. Ip_u2u1u3(_ori);
  21. --- a/arch/mips/mm/uasm-mips.c
  22. +++ b/arch/mips/mm/uasm-mips.c
  23. @@ -90,7 +90,7 @@ static const struct insn insn_table[insn
  24. RS | RT | RD},
  25. [insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
  26. [insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
  27. - [insn_dmulu] = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op),
  28. + [insn_dmulu] = {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op),
  29. RS | RT | RD},
  30. [insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
  31. [insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
  32. @@ -150,6 +150,8 @@ static const struct insn insn_table[insn
  33. [insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
  34. [insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),
  35. RS | RT | RD},
  36. + [insn_muhu] = {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op),
  37. + RS | RT | RD},
  38. #ifndef CONFIG_CPU_MIPSR6
  39. [insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
  40. #else
  41. --- a/arch/mips/mm/uasm.c
  42. +++ b/arch/mips/mm/uasm.c
  43. @@ -59,7 +59,7 @@ enum opcode {
  44. insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,
  45. insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,
  46. insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,
  47. - insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor,
  48. + insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor,
  49. insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,
  50. insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,
  51. insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
  52. @@ -344,6 +344,7 @@ I_u1(_mtlo)
  53. I_u3u1u2(_mul)
  54. I_u1u2(_multu)
  55. I_u3u1u2(_mulu)
  56. +I_u3u1u2(_muhu)
  57. I_u3u1u2(_nor)
  58. I_u3u1u2(_or)
  59. I_u2u1u3(_ori)