420-v5.19-02-mtd-spinand-gigadevice-add-support-for-GD5FxGQ4xExxG.patch 2.3 KB

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  1. From 573eec222bc82fb5e724586267fbbb1aed9ffd03 Mon Sep 17 00:00:00 2001
  2. From: Chuanhong Guo <[email protected]>
  3. Date: Sun, 20 Mar 2022 17:59:58 +0800
  4. Subject: [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG
  5. Add support for:
  6. GD5F1GQ4RExxG
  7. GD5F2GQ4{U,R}ExxG
  8. These chips differ from GD5F1GQ4UExxG only in chip ID, voltage
  9. and capacity.
  10. Signed-off-by: Chuanhong Guo <[email protected]>
  11. Signed-off-by: Miquel Raynal <[email protected]>
  12. Link: https://lore.kernel.org/linux-mtd/[email protected]
  13. ---
  14. drivers/mtd/nand/spi/gigadevice.c | 30 ++++++++++++++++++++++++++++++
  15. 1 file changed, 30 insertions(+)
  16. --- a/drivers/mtd/nand/spi/gigadevice.c
  17. +++ b/drivers/mtd/nand/spi/gigadevice.c
  18. @@ -333,6 +333,36 @@ static const struct spinand_info gigadev
  19. SPINAND_HAS_QE_BIT,
  20. SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  21. gd5fxgq4uexxg_ecc_get_status)),
  22. + SPINAND_INFO("GD5F1GQ4RExxG",
  23. + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
  24. + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
  25. + NAND_ECCREQ(8, 512),
  26. + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
  27. + &write_cache_variants,
  28. + &update_cache_variants),
  29. + SPINAND_HAS_QE_BIT,
  30. + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  31. + gd5fxgq4uexxg_ecc_get_status)),
  32. + SPINAND_INFO("GD5F2GQ4UExxG",
  33. + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
  34. + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
  35. + NAND_ECCREQ(8, 512),
  36. + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
  37. + &write_cache_variants,
  38. + &update_cache_variants),
  39. + SPINAND_HAS_QE_BIT,
  40. + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  41. + gd5fxgq4uexxg_ecc_get_status)),
  42. + SPINAND_INFO("GD5F2GQ4RExxG",
  43. + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
  44. + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
  45. + NAND_ECCREQ(8, 512),
  46. + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
  47. + &write_cache_variants,
  48. + &update_cache_variants),
  49. + SPINAND_HAS_QE_BIT,
  50. + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  51. + gd5fxgq4uexxg_ecc_get_status)),
  52. SPINAND_INFO("GD5F1GQ4UFxxG",
  53. SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
  54. NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),