qcom-ipq8064-r7500v2.dts 6.2 KB

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  1. #include "qcom-ipq8064-v2.0.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. / {
  4. model = "Netgear Nighthawk X4 R7500v2";
  5. compatible = "netgear,r7500v2", "qcom,ipq8064";
  6. memory@0 {
  7. reg = <0x42000000 0x1e000000>;
  8. device_type = "memory";
  9. };
  10. reserved-memory {
  11. rsvd@5fe00000 {
  12. reg = <0x5fe00000 0x200000>;
  13. reusable;
  14. };
  15. };
  16. aliases {
  17. mdio-gpio0 = &mdio0;
  18. led-boot = &power;
  19. led-failsafe = &power;
  20. led-running = &power;
  21. led-upgrade = &power;
  22. };
  23. chosen {
  24. bootargs = "rootfstype=squashfs noinitrd";
  25. };
  26. keys {
  27. compatible = "gpio-keys";
  28. pinctrl-0 = <&button_pins>;
  29. pinctrl-names = "default";
  30. wifi {
  31. label = "wifi";
  32. gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
  33. linux,code = <KEY_RFKILL>;
  34. debounce-interval = <60>;
  35. wakeup-source;
  36. };
  37. reset {
  38. label = "reset";
  39. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  40. linux,code = <KEY_RESTART>;
  41. debounce-interval = <60>;
  42. wakeup-source;
  43. };
  44. wps {
  45. label = "wps";
  46. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  47. linux,code = <KEY_WPS_BUTTON>;
  48. debounce-interval = <60>;
  49. wakeup-source;
  50. };
  51. };
  52. leds {
  53. compatible = "gpio-leds";
  54. pinctrl-0 = <&led_pins>;
  55. pinctrl-names = "default";
  56. usb1 {
  57. label = "amber:usb1";
  58. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  59. };
  60. usb3 {
  61. label = "amber:usb3";
  62. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  63. };
  64. status {
  65. label = "amber:status";
  66. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  67. };
  68. internet {
  69. label = "white:internet";
  70. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  71. };
  72. wan {
  73. label = "white:wan";
  74. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  75. };
  76. wps {
  77. label = "white:wps";
  78. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  79. };
  80. esata {
  81. label = "white:esata";
  82. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
  83. };
  84. power: power {
  85. label = "white:power";
  86. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
  87. default-state = "keep";
  88. };
  89. wifi {
  90. label = "white:wifi";
  91. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
  92. };
  93. };
  94. };
  95. &adm_dma {
  96. status = "okay";
  97. };
  98. &qcom_pinmux {
  99. button_pins: button_pins {
  100. mux {
  101. pins = "gpio6", "gpio54", "gpio65";
  102. function = "gpio";
  103. drive-strength = <2>;
  104. bias-pull-up;
  105. };
  106. };
  107. led_pins: led_pins {
  108. mux {
  109. pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
  110. "gpio24","gpio26", "gpio53", "gpio64";
  111. function = "gpio";
  112. drive-strength = <2>;
  113. bias-pull-up;
  114. };
  115. };
  116. usb0_pwr_en_pins: usb0_pwr_en_pins {
  117. mux {
  118. pins = "gpio15";
  119. function = "gpio";
  120. drive-strength = <12>;
  121. bias-pull-down;
  122. output-high;
  123. };
  124. };
  125. usb1_pwr_en_pins: usb1_pwr_en_pins {
  126. mux {
  127. pins = "gpio16", "gpio68";
  128. function = "gpio";
  129. drive-strength = <12>;
  130. bias-pull-down;
  131. output-high;
  132. };
  133. };
  134. };
  135. &sata_phy {
  136. status = "okay";
  137. };
  138. &sata {
  139. status = "okay";
  140. };
  141. &usb3_0 {
  142. status = "okay";
  143. pinctrl-0 = <&usb0_pwr_en_pins>;
  144. pinctrl-names = "default";
  145. };
  146. &usb3_1 {
  147. status = "okay";
  148. pinctrl-0 = <&usb1_pwr_en_pins>;
  149. pinctrl-names = "default";
  150. };
  151. &pcie0 {
  152. status = "okay";
  153. reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
  154. pinctrl-0 = <&pcie0_pins>;
  155. pinctrl-names = "default";
  156. bridge@0,0 {
  157. reg = <0x00000000 0 0 0 0>;
  158. #address-cells = <3>;
  159. #size-cells = <2>;
  160. ranges;
  161. wifi@1,0 {
  162. compatible = "pci168c,0040";
  163. reg = <0x00010000 0 0 0 0>;
  164. nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;
  165. nvmem-cell-names = "mac-address", "pre-calibration";
  166. mac-address-increment = <(1)>;
  167. };
  168. };
  169. };
  170. &pcie1 {
  171. status = "okay";
  172. reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
  173. pinctrl-0 = <&pcie1_pins>;
  174. pinctrl-names = "default";
  175. max-link-speed = <1>;
  176. bridge@0,0 {
  177. reg = <0x00000000 0 0 0 0>;
  178. #address-cells = <3>;
  179. #size-cells = <2>;
  180. ranges;
  181. wifi@1,0 {
  182. compatible = "pci168c,0040";
  183. reg = <0x00010000 0 0 0 0>;
  184. nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;
  185. nvmem-cell-names = "mac-address", "pre-calibration";
  186. mac-address-increment = <(2)>;
  187. };
  188. };
  189. };
  190. &nand {
  191. status = "okay";
  192. pinctrl-0 = <&nand_pins>;
  193. pinctrl-names = "default";
  194. nand@0 {
  195. reg = <0>;
  196. compatible = "qcom,nandcs";
  197. nand-ecc-strength = <4>;
  198. nand-bus-width = <8>;
  199. nand-ecc-step-size = <512>;
  200. nand-is-boot-medium;
  201. qcom,boot_pages_size = <0x1180000>;
  202. partitions {
  203. compatible = "fixed-partitions";
  204. #address-cells = <1>;
  205. #size-cells = <1>;
  206. qcadata@0 {
  207. label = "qcadata";
  208. reg = <0x0000000 0x0c80000>;
  209. read-only;
  210. };
  211. APPSBL@c80000 {
  212. label = "APPSBL";
  213. reg = <0x0c80000 0x0500000>;
  214. read-only;
  215. };
  216. APPSBLENV@1180000 {
  217. label = "APPSBLENV";
  218. reg = <0x1180000 0x0080000>;
  219. read-only;
  220. };
  221. art@1200000 {
  222. label = "art";
  223. reg = <0x1200000 0x0140000>;
  224. read-only;
  225. compatible = "nvmem-cells";
  226. #address-cells = <1>;
  227. #size-cells = <1>;
  228. macaddr_art_0: macaddr@0 {
  229. reg = <0x0 0x6>;
  230. };
  231. macaddr_art_6: macaddr@6 {
  232. reg = <0x6 0x6>;
  233. };
  234. precal_art_1000: precal@1000 {
  235. reg = <0x1000 0x2f20>;
  236. };
  237. precal_art_5000: precal@5000 {
  238. reg = <0x5000 0x2f20>;
  239. };
  240. };
  241. artbak: art@1340000 {
  242. label = "artbak";
  243. reg = <0x1340000 0x0140000>;
  244. read-only;
  245. };
  246. kernel@1480000 {
  247. label = "kernel";
  248. reg = <0x1480000 0x0400000>;
  249. };
  250. ubi@1880000 {
  251. label = "ubi";
  252. reg = <0x1880000 0x6080000>;
  253. };
  254. reserve@7900000 {
  255. label = "reserve";
  256. reg = <0x7900000 0x0700000>;
  257. read-only;
  258. };
  259. };
  260. };
  261. };
  262. &mdio0 {
  263. status = "okay";
  264. pinctrl-0 = <&mdio0_pins>;
  265. pinctrl-names = "default";
  266. phy0: ethernet-phy@0 {
  267. reg = <0>;
  268. qca,ar8327-initvals = <
  269. 0x00004 0x7600000 /* PAD0_MODE */
  270. 0x00008 0x1000000 /* PAD5_MODE */
  271. 0x0000c 0x80 /* PAD6_MODE */
  272. 0x000e4 0xaa545 /* MAC_POWER_SEL */
  273. 0x000e0 0xc74164de /* SGMII_CTRL */
  274. 0x0007c 0x4e /* PORT0_STATUS */
  275. 0x00094 0x4e /* PORT6_STATUS */
  276. >;
  277. };
  278. phy4: ethernet-phy@4 {
  279. reg = <4>;
  280. };
  281. };
  282. &gmac1 {
  283. status = "okay";
  284. phy-mode = "rgmii";
  285. qcom,id = <1>;
  286. pinctrl-0 = <&rgmii2_pins>;
  287. pinctrl-names = "default";
  288. nvmem-cells = <&macaddr_art_6>;
  289. nvmem-cell-names = "mac-address";
  290. fixed-link {
  291. speed = <1000>;
  292. full-duplex;
  293. };
  294. };
  295. &gmac2 {
  296. status = "okay";
  297. phy-mode = "sgmii";
  298. qcom,id = <2>;
  299. nvmem-cells = <&macaddr_art_0>;
  300. nvmem-cell-names = "mac-address";
  301. fixed-link {
  302. speed = <1000>;
  303. full-duplex;
  304. };
  305. };