qcom-ipq8065-rt4230w-rev6.dts 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. #include "qcom-ipq8065.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. model = "Askey RT4230W REV6";
  6. compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
  7. memory@0 {
  8. reg = <0x42000000 0x3e000000>;
  9. device_type = "memory";
  10. };
  11. aliases {
  12. led-boot = &ledctrl3;
  13. led-failsafe = &ledctrl1;
  14. led-running = &ledctrl2;
  15. led-upgrade = &ledctrl3;
  16. };
  17. chosen {
  18. bootargs = "rootfstype=squashfs noinitrd";
  19. };
  20. keys {
  21. compatible = "gpio-keys";
  22. pinctrl-0 = <&button_pins>;
  23. pinctrl-names = "default";
  24. reset {
  25. label = "reset";
  26. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  27. linux,code = <KEY_RESTART>;
  28. };
  29. wps {
  30. label = "wps";
  31. gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  32. linux,code = <KEY_WPS_BUTTON>;
  33. };
  34. };
  35. leds {
  36. compatible = "gpio-leds";
  37. pinctrl-0 = <&led_pins>;
  38. pinctrl-names = "default";
  39. ledctrl1: ledctrl1 {
  40. label = "ledctrl1";
  41. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  42. };
  43. ledctrl2: ledctrl2 {
  44. label = "ledctrl2";
  45. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  46. };
  47. ledctrl3: ledctrl3 {
  48. label = "ledctrl3";
  49. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  50. };
  51. };
  52. };
  53. &qcom_pinmux {
  54. button_pins: button_pins {
  55. mux {
  56. pins = "gpio54", "gpio68";
  57. function = "gpio";
  58. drive-strength = <2>;
  59. bias-pull-up;
  60. };
  61. };
  62. led_pins: led_pins {
  63. mux {
  64. pins = "gpio22", "gpio23", "gpio24";
  65. function = "gpio";
  66. drive-strength = <2>;
  67. bias-pull-down;
  68. };
  69. };
  70. rgmii2_pins: rgmii2_pins {
  71. mux {
  72. pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
  73. "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
  74. function = "rgmii2";
  75. drive-strength = <8>;
  76. bias-disable;
  77. };
  78. tx {
  79. pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
  80. input-disable;
  81. };
  82. };
  83. spi_pins: spi_pins {
  84. cs {
  85. pins = "gpio20";
  86. drive-strength = <12>;
  87. };
  88. };
  89. };
  90. &gsbi5 {
  91. qcom,mode = <GSBI_PROT_SPI>;
  92. status = "okay";
  93. spi@1a280000 {
  94. status = "okay";
  95. pinctrl-0 = <&spi_pins>;
  96. pinctrl-names = "default";
  97. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  98. flash@0 {
  99. compatible = "everspin,mr25h256";
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. spi-max-frequency = <40000000>;
  103. reg = <0>;
  104. };
  105. };
  106. };
  107. &nand {
  108. status = "okay";
  109. pinctrl-0 = <&nand_pins>;
  110. pinctrl-names = "default";
  111. nand@0 {
  112. reg = <0>;
  113. compatible = "qcom,nandcs";
  114. nand-ecc-strength = <4>;
  115. nand-bus-width = <8>;
  116. nand-ecc-step-size = <512>;
  117. partitions {
  118. compatible = "fixed-partitions";
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. partition@0 {
  122. label = "0:SBL1";
  123. reg = <0x0000000 0x0040000>;
  124. read-only;
  125. };
  126. partition@40000 {
  127. label = "0:MIBIB";
  128. reg = <0x0040000 0x0140000>;
  129. read-only;
  130. };
  131. partition@180000 {
  132. label = "0:SBL2";
  133. reg = <0x0180000 0x0140000>;
  134. read-only;
  135. };
  136. partition@2c0000 {
  137. label = "0:SBL3";
  138. reg = <0x02c0000 0x0280000>;
  139. read-only;
  140. };
  141. partition@540000 {
  142. label = "0:DDRCONFIG";
  143. reg = <0x0540000 0x0120000>;
  144. read-only;
  145. };
  146. partition@660000 {
  147. label = "0:SSD";
  148. reg = <0x0660000 0x0120000>;
  149. read-only;
  150. };
  151. partition@780000 {
  152. label = "0:TZ";
  153. reg = <0x0780000 0x0280000>;
  154. read-only;
  155. };
  156. partition@a00000 {
  157. label = "0:RPM";
  158. reg = <0x0a00000 0x0280000>;
  159. read-only;
  160. };
  161. partition@c80000 {
  162. label = "0:APPSBL";
  163. reg = <0x0c80000 0x0500000>;
  164. read-only;
  165. };
  166. partition@1180000 {
  167. label = "0:APPSBLENV";
  168. reg = <0x1180000 0x0080000>;
  169. };
  170. partition@1200000 {
  171. label = "0:ART";
  172. reg = <0x1200000 0x0140000>;
  173. read-only;
  174. compatible = "nvmem-cells";
  175. #address-cells = <1>;
  176. #size-cells = <1>;
  177. macaddr_ART_0: macaddr@0 {
  178. reg = <0x0 0x6>;
  179. };
  180. macaddr_ART_6: macaddr@6 {
  181. reg = <0x6 0x6>;
  182. };
  183. precal_ART_1000: precal@1000 {
  184. reg = <0x1000 0x2f20>;
  185. };
  186. precal_ART_5000: precal@5000 {
  187. reg = <0x5000 0x2f20>;
  188. };
  189. };
  190. partition@1340000 {
  191. label = "0:BOOTCONFIG";
  192. reg = <0x1340000 0x0060000>;
  193. read-only;
  194. };
  195. partition@13a0000 {
  196. label = "0:SBL2_1";
  197. reg = <0x13a0000 0x0140000>;
  198. read-only;
  199. };
  200. partition@14e0000 {
  201. label = "0:SBL3_1";
  202. reg = <0x14e0000 0x0280000>;
  203. read-only;
  204. };
  205. partition@1760000 {
  206. label = "0:DDRCONFIG_1";
  207. reg = <0x1760000 0x0120000>;
  208. read-only;
  209. };
  210. partition@1880000 {
  211. label = "0:SSD_1";
  212. reg = <0x1880000 0x0120000>;
  213. read-only;
  214. };
  215. partition@19a0000 {
  216. label = "0:TZ_1";
  217. reg = <0x19a0000 0x0280000>;
  218. read-only;
  219. };
  220. partition@1c20000 {
  221. label = "0:RPM_1";
  222. reg = <0x1c20000 0x0280000>;
  223. read-only;
  224. };
  225. partition@1ea0000 {
  226. label = "0:BOOTCONFIG1";
  227. reg = <0x1ea0000 0x0060000>;
  228. read-only;
  229. };
  230. partition@1f00000 {
  231. label = "0:APPSBL_1";
  232. reg = <0x1f00000 0x0500000>;
  233. read-only;
  234. };
  235. partition@2400000 {
  236. label = "ubi";
  237. reg = <0x2400000 0x1a000000>;
  238. };
  239. };
  240. };
  241. };
  242. &mdio0 {
  243. status = "okay";
  244. pinctrl-0 = <&mdio0_pins>;
  245. pinctrl-names = "default";
  246. phy0: ethernet-phy@0 {
  247. reg = <0x0>;
  248. qca,ar8327-initvals = <
  249. 0x00004 0x7600000 /* PAD0_MODE */
  250. 0x00008 0x1000000 /* PAD5_MODE */
  251. 0x0000c 0x80 /* PAD6_MODE */
  252. 0x000e4 0xaa545 /* MAC_POWER_SEL */
  253. 0x000e0 0xc74164de /* SGMII_CTRL */
  254. 0x0007c 0x4e /* PORT0_STATUS */
  255. 0x00094 0x4e /* PORT6_STATUS */
  256. 0x00050 0xcf02cf02 /* LED_CTRL_0 */
  257. 0x00054 0xc832c832 /* LED_CTRL_1 */
  258. >;
  259. };
  260. };
  261. &gmac0 {
  262. status = "okay";
  263. phy-mode = "rgmii";
  264. qcom,id = <0>;
  265. nvmem-cells = <&macaddr_ART_0>;
  266. nvmem-cell-names = "mac-address";
  267. pinctrl-0 = <&rgmii2_pins>;
  268. pinctrl-names = "default";
  269. fixed-link {
  270. speed = <1000>;
  271. full-duplex;
  272. };
  273. };
  274. &gmac1 {
  275. status = "okay";
  276. phy-mode = "sgmii";
  277. qcom,id = <1>;
  278. nvmem-cells = <&macaddr_ART_6>;
  279. nvmem-cell-names = "mac-address";
  280. fixed-link {
  281. speed = <1000>;
  282. full-duplex;
  283. };
  284. };
  285. &adm_dma {
  286. status = "okay";
  287. };
  288. &usb3_0 {
  289. status = "okay";
  290. };
  291. &usb3_1 {
  292. status = "okay";
  293. };
  294. &pcie0 {
  295. status = "okay";
  296. reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
  297. pinctrl-0 = <&pcie0_pins>;
  298. pinctrl-names = "default";
  299. bridge@0,0 {
  300. reg = <0x00000000 0 0 0 0>;
  301. #address-cells = <3>;
  302. #size-cells = <2>;
  303. ranges;
  304. wifi0: wifi@1,0 {
  305. compatible = "pci168c,0046";
  306. reg = <0x00010000 0 0 0 0>;
  307. nvmem-cells = <&precal_ART_1000>;
  308. nvmem-cell-names = "pre-calibration";
  309. };
  310. };
  311. };
  312. &pcie1 {
  313. status = "okay";
  314. reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
  315. pinctrl-0 = <&pcie1_pins>;
  316. pinctrl-names = "default";
  317. max-link-speed = <1>;
  318. bridge@0,0 {
  319. reg = <0x00000000 0 0 0 0>;
  320. #address-cells = <3>;
  321. #size-cells = <2>;
  322. ranges;
  323. wifi1: wifi@1,0 {
  324. compatible = "pci168c,0046";
  325. reg = <0x00010000 0 0 0 0>;
  326. nvmem-cells = <&precal_ART_5000>;
  327. nvmem-cell-names = "pre-calibration";
  328. };
  329. };
  330. };