2
0

729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch 2.0 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970
  1. From: Lorenzo Bianconi <[email protected]>
  2. Date: Sat, 14 Jan 2023 18:01:28 +0100
  3. Subject: [PATCH] net: ethernet: mtk_eth_soc: introduce mtk_hw_reset utility
  4. routine
  5. This is a preliminary patch to add Wireless Ethernet Dispatcher reset
  6. support.
  7. Reviewed-by: Leon Romanovsky <[email protected]>
  8. Tested-by: Daniel Golle <[email protected]>
  9. Co-developed-by: Sujuan Chen <[email protected]>
  10. Signed-off-by: Sujuan Chen <[email protected]>
  11. Signed-off-by: Lorenzo Bianconi <[email protected]>
  12. Signed-off-by: Paolo Abeni <[email protected]>
  13. ---
  14. --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  15. +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  16. @@ -3202,6 +3202,27 @@ static void mtk_set_mcr_max_rx(struct mt
  17. mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
  18. }
  19. +static void mtk_hw_reset(struct mtk_eth *eth)
  20. +{
  21. + u32 val;
  22. +
  23. + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  24. + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
  25. + val = RSTCTRL_PPE0_V2;
  26. + } else {
  27. + val = RSTCTRL_PPE0;
  28. + }
  29. +
  30. + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  31. + val |= RSTCTRL_PPE1;
  32. +
  33. + ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
  34. +
  35. + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
  36. + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  37. + 0x3ffffff);
  38. +}
  39. +
  40. static int mtk_hw_init(struct mtk_eth *eth)
  41. {
  42. u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
  43. @@ -3241,22 +3262,9 @@ static int mtk_hw_init(struct mtk_eth *e
  44. return 0;
  45. }
  46. - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  47. - regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
  48. - val = RSTCTRL_PPE0_V2;
  49. - } else {
  50. - val = RSTCTRL_PPE0;
  51. - }
  52. -
  53. - if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
  54. - val |= RSTCTRL_PPE1;
  55. -
  56. - ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
  57. + mtk_hw_reset(eth);
  58. if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  59. - regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  60. - 0x3ffffff);
  61. -
  62. /* Set FE to PDMAv2 if necessary */
  63. val = mtk_r32(eth, MTK_FE_GLO_MISC);
  64. mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);