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- From c0a440031d4314d1023c1b87f43a4233634eebdb Mon Sep 17 00:00:00 2001
- From: Daniel Golle <[email protected]>
- Date: Sun, 19 Mar 2023 12:57:15 +0000
- Subject: [PATCH] net: ethernet: mtk_eth_soc: set MDIO bus clock frequency
- MIME-Version: 1.0
- Content-Type: text/plain; charset=UTF-8
- Content-Transfer-Encoding: 8bit
- Set MDIO bus clock frequency and allow setting a custom maximum
- frequency from device tree.
- Reviewed-by: Andrew Lunn <[email protected]>
- Reviewed-by: Florian Fainelli <[email protected]>
- Tested-by: Bjørn Mork <[email protected]>
- Signed-off-by: Daniel Golle <[email protected]>
- Signed-off-by: Jakub Kicinski <[email protected]>
- ---
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 21 +++++++++++++++++++++
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 7 +++++++
- 2 files changed, 28 insertions(+)
- --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
- +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
- @@ -701,8 +701,10 @@ static const struct phylink_mac_ops mtk_
-
- static int mtk_mdio_init(struct mtk_eth *eth)
- {
- + unsigned int max_clk = 2500000, divider;
- struct device_node *mii_np;
- int ret;
- + u32 val;
-
- mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
- if (!mii_np) {
- @@ -728,6 +730,25 @@ static int mtk_mdio_init(struct mtk_eth
- eth->mii_bus->parent = eth->dev;
-
- snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
- +
- + if (!of_property_read_u32(mii_np, "clock-frequency", &val)) {
- + if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
- + dev_err(eth->dev, "MDIO clock frequency out of range");
- + ret = -EINVAL;
- + goto err_put_node;
- + }
- + max_clk = val;
- + }
- + divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
- +
- + /* Configure MDC Divider */
- + val = mtk_r32(eth, MTK_PPSC);
- + val &= ~PPSC_MDC_CFG;
- + val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
- + mtk_w32(eth, val, MTK_PPSC);
- +
- + dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
- +
- ret = of_mdiobus_register(eth->mii_bus, mii_np);
-
- err_put_node:
- --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
- +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
- @@ -363,6 +363,13 @@
- #define RX_DMA_VTAG_V2 BIT(0)
- #define RX_DMA_L4_VALID_V2 BIT(2)
-
- +/* PHY Polling and SMI Master Control registers */
- +#define MTK_PPSC 0x10000
- +#define PPSC_MDC_CFG GENMASK(29, 24)
- +#define PPSC_MDC_TURBO BIT(20)
- +#define MDC_MAX_FREQ 25000000
- +#define MDC_MAX_DIVIDER 63
- +
- /* PHY Indirect Access Control registers */
- #define MTK_PHY_IAC 0x10004
- #define PHY_IAC_ACCESS BIT(31)
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