bcm6328.dtsi 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /dts-v1/;
  3. #include <dt-bindings/clock/bcm6328-clock.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/interrupt-controller/bcm6328-interrupt-controller.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/leds/common.h>
  9. #include <dt-bindings/reset/bcm6328-reset.h>
  10. #include <dt-bindings/soc/bcm6328-pm.h>
  11. / {
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. compatible = "brcm,bcm6328";
  15. aliases {
  16. nflash = &nflash;
  17. pinctrl = &pinctrl;
  18. serial0 = &uart0;
  19. serial1 = &uart1;
  20. spi1 = &hsspi;
  21. };
  22. chosen {
  23. bootargs = "earlycon";
  24. stdout-path = "serial0:115200n8";
  25. };
  26. clocks {
  27. periph_osc: periph-osc {
  28. compatible = "fixed-clock";
  29. #clock-cells = <0>;
  30. clock-frequency = <50000000>;
  31. clock-output-names = "periph";
  32. };
  33. hsspi_osc: hsspi-osc {
  34. compatible = "fixed-clock";
  35. #clock-cells = <0>;
  36. clock-frequency = <133333333>;
  37. clock-output-names = "hsspi_osc";
  38. };
  39. };
  40. cpus {
  41. #address-cells = <1>;
  42. #size-cells = <0>;
  43. mips-hpt-frequency = <160000000>;
  44. cpu@0 {
  45. compatible = "brcm,bmips4350", "mips,mips4Kc";
  46. device_type = "cpu";
  47. reg = <0>;
  48. };
  49. cpu@1 {
  50. compatible = "brcm,bmips4350", "mips,mips4Kc";
  51. device_type = "cpu";
  52. reg = <1>;
  53. };
  54. };
  55. cpu_intc: interrupt-controller {
  56. #address-cells = <0>;
  57. compatible = "mti,cpu-interrupt-controller";
  58. interrupt-controller;
  59. #interrupt-cells = <1>;
  60. };
  61. memory@0 {
  62. device_type = "memory";
  63. reg = <0 0>;
  64. };
  65. ubus {
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. compatible = "simple-bus";
  69. ranges;
  70. periph_clk: clock-controller@10000004 {
  71. compatible = "brcm,bcm6328-clocks";
  72. reg = <0x10000004 0x4>;
  73. #clock-cells = <1>;
  74. };
  75. periph_rst: reset-controller@10000010 {
  76. compatible = "brcm,bcm6345-reset";
  77. reg = <0x10000010 0x4>;
  78. #reset-cells = <1>;
  79. };
  80. ext_intc: interrupt-controller@10000018 {
  81. #address-cells = <1>;
  82. compatible = "brcm,bcm6345-ext-intc";
  83. reg = <0x10000018 0x4>;
  84. interrupt-controller;
  85. #interrupt-cells = <2>;
  86. interrupt-parent = <&periph_intc>;
  87. interrupts = <BCM6328_IRQ_EXTO>,
  88. <BCM6328_IRQ_EXT1>,
  89. <BCM6328_IRQ_EXT2>,
  90. <BCM6328_IRQ_EXT3>;
  91. };
  92. periph_intc: interrupt-controller@10000020 {
  93. #address-cells = <1>;
  94. compatible = "brcm,bcm6345-l1-intc";
  95. reg = <0x10000020 0x10>,
  96. <0x10000030 0x10>;
  97. interrupt-controller;
  98. #interrupt-cells = <1>;
  99. interrupt-parent = <&cpu_intc>;
  100. interrupts = <2>, <3>;
  101. };
  102. wdt: watchdog@1000005c {
  103. compatible = "brcm,bcm7038-wdt";
  104. reg = <0x1000005c 0xc>;
  105. clocks = <&periph_osc>;
  106. timeout-sec = <30>;
  107. };
  108. pll_cntl: syscon@10000068 {
  109. compatible = "syscon", "simple-mfd";
  110. reg = <0x10000068 0x4>;
  111. native-endian;
  112. syscon-reboot {
  113. compatible = "syscon-reboot";
  114. offset = <0>;
  115. mask = <0x1>;
  116. };
  117. };
  118. gpio_cntl: syscon@10000080 {
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. compatible = "brcm,bcm6328-gpio-sysctl",
  122. "syscon", "simple-mfd";
  123. reg = <0x10000080 0x80>;
  124. ranges = <0 0x10000080 0x80>;
  125. native-endian;
  126. gpio: gpio@0 {
  127. compatible = "brcm,bcm6328-gpio";
  128. reg-names = "dirout", "dat";
  129. reg = <0x0 0x8>, <0x8 0x8>;
  130. gpio-controller;
  131. gpio-ranges = <&pinctrl 0 0 32>;
  132. #gpio-cells = <2>;
  133. };
  134. pinctrl: pinctrl@18 {
  135. compatible = "brcm,bcm6328-pinctrl";
  136. reg = <0x18 0x10>;
  137. pinctrl_serial_led: serial_led-pins {
  138. pinctrl_serial_led_data: serial_led_data-pins {
  139. function = "serial_led_data";
  140. pins = "gpio6";
  141. };
  142. pinctrl_serial_led_clk: serial_led_clk-pins {
  143. function = "serial_led_clk";
  144. pins = "gpio7";
  145. };
  146. };
  147. pinctrl_inet_act_led: inet_act_led-pins {
  148. function = "inet_act_led";
  149. pins = "gpio11";
  150. };
  151. pinctrl_pcie_clkreq: pcie_clkreq-pins {
  152. function = "pcie_clkreq";
  153. pins = "gpio16";
  154. };
  155. pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
  156. function = "led";
  157. pins = "gpio17";
  158. };
  159. pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
  160. function = "led";
  161. pins = "gpio18";
  162. };
  163. pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
  164. function = "led";
  165. pins = "gpio19";
  166. };
  167. pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
  168. function = "led";
  169. pins = "gpio20";
  170. };
  171. pinctrl_ephy0_act_led: ephy0_act_led-pins {
  172. function = "ephy0_act_led";
  173. pins = "gpio25";
  174. };
  175. pinctrl_ephy1_act_led: ephy1_act_led-pins {
  176. function = "ephy1_act_led";
  177. pins = "gpio26";
  178. };
  179. pinctrl_ephy2_act_led: ephy2_act_led-pins {
  180. function = "ephy2_act_led";
  181. pins = "gpio27";
  182. };
  183. pinctrl_ephy3_act_led: ephy3_act_led-pins {
  184. function = "ephy3_act_led";
  185. pins = "gpio28";
  186. };
  187. pinctrl_hsspi_cs1: hsspi_cs1-pins {
  188. function = "hsspi_cs1";
  189. pins = "hsspi_cs1";
  190. };
  191. pinctrl_usb_port1_device: usb_port1_device-pins {
  192. function = "usb_device_port";
  193. pins = "usb_port1";
  194. };
  195. pinctrl_usb_port1_host: usb_port1_host-pins {
  196. function = "usb_host_port";
  197. pins = "usb_port1";
  198. };
  199. };
  200. };
  201. uart0: serial@10000100 {
  202. compatible = "brcm,bcm6345-uart";
  203. reg = <0x10000100 0x18>;
  204. interrupt-parent = <&periph_intc>;
  205. interrupts = <BCM6328_IRQ_UART0>;
  206. clocks = <&periph_osc>;
  207. clock-names = "periph";
  208. status = "disabled";
  209. };
  210. uart1: serial@10000120 {
  211. compatible = "brcm,bcm6345-uart";
  212. reg = <0x10000120 0x18>;
  213. interrupt-parent = <&periph_intc>;
  214. interrupts = <BCM6328_IRQ_UART1>;
  215. clocks = <&periph_osc>;
  216. clock-names = "periph";
  217. status = "disabled";
  218. };
  219. nflash: nand@10000200 {
  220. #address-cells = <1>;
  221. #size-cells = <0>;
  222. compatible = "brcm,nand-bcm6368",
  223. "brcm,brcmnand-v2.2",
  224. "brcm,brcmnand";
  225. reg = <0x10000200 0x180>,
  226. <0x10000400 0x200>,
  227. <0x10000070 0x10>;
  228. reg-names = "nand",
  229. "nand-cache",
  230. "nand-int-base";
  231. interrupt-parent = <&periph_intc>;
  232. interrupts = <BCM6328_IRQ_NAND>;
  233. status = "disabled";
  234. };
  235. leds: led-controller@10000800 {
  236. #address-cells = <1>;
  237. #size-cells = <0>;
  238. compatible = "brcm,bcm6328-leds";
  239. reg = <0x10000800 0x24>;
  240. status = "disabled";
  241. };
  242. hsspi: spi@10001000 {
  243. #address-cells = <1>;
  244. #size-cells = <0>;
  245. compatible = "brcm,bcm6328-hsspi";
  246. reg = <0x10001000 0x600>;
  247. interrupt-parent = <&periph_intc>;
  248. interrupts = <BCM6328_IRQ_HSSPI>;
  249. clocks = <&periph_clk BCM6328_CLK_HSSPI>,
  250. <&hsspi_osc>;
  251. clock-names = "hsspi",
  252. "pll";
  253. resets = <&periph_rst BCM6328_RST_SPI>;
  254. status = "disabled";
  255. };
  256. serdes_cntl: syscon@10001800 {
  257. compatible = "syscon";
  258. reg = <0x10001800 0x4>;
  259. native-endian;
  260. };
  261. periph_pwr: power-controller@10001848 {
  262. compatible = "brcm,bcm6328-power-controller";
  263. reg = <0x10001848 0x4>;
  264. #power-domain-cells = <1>;
  265. };
  266. ehci: usb@10002500 {
  267. compatible = "brcm,bcm6328-ehci", "generic-ehci";
  268. reg = <0x10002500 0x100>;
  269. big-endian;
  270. spurious-oc;
  271. interrupt-parent = <&periph_intc>;
  272. interrupts = <BCM6328_IRQ_EHCI>;
  273. phys = <&usbh 0>;
  274. phy-names = "usb";
  275. status = "disabled";
  276. };
  277. ohci: usb@10002600 {
  278. compatible = "brcm,bcm6328-ohci", "generic-ohci";
  279. reg = <0x10002600 0x100>;
  280. big-endian;
  281. no-big-frame-no;
  282. interrupt-parent = <&periph_intc>;
  283. interrupts = <BCM6328_IRQ_OHCI>;
  284. phys = <&usbh 0>;
  285. phy-names = "usb";
  286. status = "disabled";
  287. };
  288. usbh: usb-phy@10002700 {
  289. compatible = "brcm,bcm6328-usbh-phy";
  290. reg = <0x10002700 0x38>;
  291. #phy-cells = <1>;
  292. clocks = <&periph_clk BCM6328_CLK_USBH>;
  293. clock-names = "usbh";
  294. power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_USBH>;
  295. resets = <&periph_rst BCM6328_RST_USBH>;
  296. status = "disabled";
  297. };
  298. ethernet: ethernet@1000d800 {
  299. compatible = "brcm,bcm6328-enetsw";
  300. reg = <0x1000d800 0x80>,
  301. <0x1000da00 0x80>,
  302. <0x1000dc00 0x80>;
  303. reg-names = "dma",
  304. "dma-channels",
  305. "dma-sram";
  306. interrupt-parent = <&periph_intc>;
  307. interrupts = <BCM6328_IRQ_ENETSW_RX_DMA0>,
  308. <BCM6328_IRQ_ENETSW_TX_DMA0>;
  309. interrupt-names = "rx",
  310. "tx";
  311. clocks = <&periph_clk BCM6328_CLK_ROBOSW>;
  312. resets = <&periph_rst BCM6328_RST_ENETSW>,
  313. <&periph_rst BCM6328_RST_EPHY>;
  314. power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_ROBOSW>,
  315. <&periph_pwr BCM6328_POWER_DOMAIN_EPHY>;
  316. dma-rx = <0>;
  317. dma-tx = <1>;
  318. status = "disabled";
  319. };
  320. switch0: switch@10e00000 {
  321. #address-cells = <1>;
  322. #size-cells = <0>;
  323. compatible = "brcm,bcm6328-switch";
  324. reg = <0x10e00000 0x8000>;
  325. big-endian;
  326. ports {
  327. #address-cells = <1>;
  328. #size-cells = <0>;
  329. port@8 {
  330. reg = <8>;
  331. phy-mode = "internal";
  332. ethernet = <&ethernet>;
  333. fixed-link {
  334. speed = <1000>;
  335. full-duplex;
  336. };
  337. };
  338. };
  339. };
  340. mdio: mdio@10e000b0 {
  341. #address-cells = <1>;
  342. #size-cells = <0>;
  343. compatible = "brcm,bcm6368-mdio-mux";
  344. reg = <0x10e000b0 0x8>;
  345. mdio_int: mdio@0 {
  346. #address-cells = <1>;
  347. #size-cells = <0>;
  348. reg = <0>;
  349. phy1: ethernet-phy@1 {
  350. compatible = "ethernet-phy-ieee802.3-c22";
  351. reg = <1>;
  352. };
  353. phy2: ethernet-phy@2 {
  354. compatible = "ethernet-phy-ieee802.3-c22";
  355. reg = <2>;
  356. };
  357. phy3: ethernet-phy@3 {
  358. compatible = "ethernet-phy-ieee802.3-c22";
  359. reg = <3>;
  360. };
  361. phy4: ethernet-phy@4 {
  362. compatible = "ethernet-phy-ieee802.3-c22";
  363. reg = <4>;
  364. };
  365. };
  366. mdio_ext: mdio@1 {
  367. #address-cells = <1>;
  368. #size-cells = <0>;
  369. reg = <1>;
  370. };
  371. };
  372. pcie: pcie@10e40000 {
  373. compatible = "brcm,bcm6328-pcie";
  374. reg = <0x10e40000 0x10000>;
  375. #address-cells = <3>;
  376. #size-cells = <2>;
  377. device_type = "pci";
  378. bus-range = <0x00 0x01>;
  379. ranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;
  380. linux,pci-probe-only = <1>;
  381. interrupt-parent = <&periph_intc>;
  382. interrupts = <BCM6328_IRQ_PCIE_RC>;
  383. clocks = <&periph_clk BCM6328_CLK_PCIE>;
  384. clock-names = "pcie";
  385. resets = <&periph_rst BCM6328_RST_PCIE>,
  386. <&periph_rst BCM6328_RST_PCIE_EXT>,
  387. <&periph_rst BCM6328_RST_PCIE_CORE>,
  388. <&periph_rst BCM6328_RST_PCIE_HARD>;
  389. reset-names = "pcie",
  390. "pcie-ext",
  391. "pcie-core",
  392. "pcie-hard";
  393. power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_PCIE>;
  394. brcm,serdes = <&serdes_cntl>;
  395. status = "disabled";
  396. };
  397. };
  398. };