bcm6368.dtsi 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /dts-v1/;
  3. #include <dt-bindings/clock/bcm6368-clock.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/leds/common.h>
  9. #include <dt-bindings/reset/bcm6368-reset.h>
  10. / {
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. compatible = "brcm,bcm6368";
  14. aliases {
  15. nflash = &nflash;
  16. pflash = &pflash;
  17. pinctrl = &pinctrl;
  18. serial0 = &uart0;
  19. serial1 = &uart1;
  20. spi0 = &lsspi;
  21. };
  22. chosen {
  23. bootargs = "earlycon";
  24. stdout-path = "serial0:115200n8";
  25. };
  26. clocks {
  27. periph_osc: periph-osc {
  28. compatible = "fixed-clock";
  29. #clock-cells = <0>;
  30. clock-frequency = <50000000>;
  31. clock-output-names = "periph";
  32. };
  33. };
  34. cpus {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. brcm,bmips-cbr-reg = <0xff400000>;
  38. mips-hpt-frequency = <200000000>;
  39. cpu@0 {
  40. compatible = "brcm,bmips4350", "mips,mips4Kc";
  41. device_type = "cpu";
  42. reg = <0>;
  43. };
  44. cpu@1 {
  45. compatible = "brcm,bmips4350", "mips,mips4Kc";
  46. device_type = "cpu";
  47. reg = <1>;
  48. };
  49. };
  50. cpu_intc: interrupt-controller {
  51. #address-cells = <0>;
  52. compatible = "mti,cpu-interrupt-controller";
  53. interrupt-controller;
  54. #interrupt-cells = <1>;
  55. };
  56. memory@0 {
  57. device_type = "memory";
  58. reg = <0 0>;
  59. };
  60. ubus {
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. compatible = "simple-bus";
  64. ranges;
  65. periph_clk: clock-controller@10000004 {
  66. compatible = "brcm,bcm6368-clocks";
  67. reg = <0x10000004 0x4>;
  68. #clock-cells = <1>;
  69. };
  70. pll_cntl: syscon@10000008 {
  71. compatible = "syscon", "simple-mfd";
  72. reg = <0x10000008 0x4>;
  73. native-endian;
  74. syscon-reboot {
  75. compatible = "syscon-reboot";
  76. offset = <0x0>;
  77. mask = <0x1>;
  78. };
  79. };
  80. periph_rst: reset-controller@10000010 {
  81. compatible = "brcm,bcm6345-reset";
  82. reg = <0x10000010 0x4>;
  83. #reset-cells = <1>;
  84. };
  85. ext_intc0: interrupt-controller@10000018 {
  86. #address-cells = <1>;
  87. compatible = "brcm,bcm6345-ext-intc";
  88. reg = <0x10000018 0x4>;
  89. interrupt-controller;
  90. #interrupt-cells = <2>;
  91. interrupt-parent = <&periph_intc>;
  92. interrupts = <BCM6368_IRQ_EXT0>,
  93. <BCM6368_IRQ_EXT1>,
  94. <BCM6368_IRQ_EXT2>,
  95. <BCM6368_IRQ_EXT3>;
  96. };
  97. ext_intc1: interrupt-controller@1000001c {
  98. #address-cells = <1>;
  99. compatible = "brcm,bcm6345-ext-intc";
  100. reg = <0x1000001c 0x4>;
  101. interrupt-controller;
  102. #interrupt-cells = <2>;
  103. interrupt-parent = <&periph_intc>;
  104. interrupts = <BCM6368_IRQ_EXT4>,
  105. <BCM6368_IRQ_EXT5>;
  106. };
  107. periph_intc: interrupt-controller@10000020 {
  108. #address-cells = <1>;
  109. compatible = "brcm,bcm6345-l1-intc";
  110. reg = <0x10000020 0x10>,
  111. <0x10000030 0x10>;
  112. interrupt-controller;
  113. #interrupt-cells = <1>;
  114. interrupt-parent = <&cpu_intc>;
  115. interrupts = <2>, <3>;
  116. };
  117. wdt: watchdog@1000005c {
  118. compatible = "brcm,bcm7038-wdt";
  119. reg = <0x1000005c 0xc>;
  120. clocks = <&periph_osc>;
  121. timeout-sec = <30>;
  122. };
  123. gpio_cntl: syscon@10000080 {
  124. #address-cells = <1>;
  125. #size-cells = <1>;
  126. compatible = "brcm,bcm6368-gpio-sysctl",
  127. "syscon", "simple-mfd";
  128. reg = <0x10000080 0x80>;
  129. ranges = <0 0x10000080 0x80>;
  130. native-endian;
  131. gpio: gpio@0 {
  132. compatible = "brcm,bcm6368-gpio";
  133. reg-names = "dirout", "dat";
  134. reg = <0x0 0x8>, <0x8 0x8>;
  135. gpio-controller;
  136. gpio-ranges = <&pinctrl 0 0 38>;
  137. #gpio-cells = <2>;
  138. };
  139. pinctrl: pinctrl@18 {
  140. compatible = "brcm,bcm6368-pinctrl";
  141. reg = <0x18 0x4>, <0x38 0x4>;
  142. pinctrl_analog_afe_0: analog_afe_0-pins {
  143. function = "analog_afe_0";
  144. pins = "gpio0";
  145. };
  146. pinctrl_analog_afe_1: analog_afe_1-pins {
  147. function = "analog_afe_1";
  148. pins = "gpio1";
  149. };
  150. pinctrl_sys_irq: sys_irq-pins {
  151. function = "sys_irq";
  152. pins = "gpio2";
  153. };
  154. pinctrl_serial_led: serial_led-pins {
  155. pinctrl_serial_led_data: serial_led_data-pins {
  156. function = "serial_led_data";
  157. pins = "gpio3";
  158. };
  159. pinctrl_serial_led_clk: serial_led_clk-pins {
  160. function = "serial_led_clk";
  161. pins = "gpio4";
  162. };
  163. };
  164. pinctrl_inet_led: inet_led-pins {
  165. function = "inet_led";
  166. pins = "gpio5";
  167. };
  168. pinctrl_ephy0_led: ephy0_led-pins {
  169. function = "ephy0_led";
  170. pins = "gpio6";
  171. };
  172. pinctrl_ephy1_led: ephy1_led-pins {
  173. function = "ephy1_led";
  174. pins = "gpio7";
  175. };
  176. pinctrl_ephy2_led: ephy2_led-pins {
  177. function = "ephy2_led";
  178. pins = "gpio8";
  179. };
  180. pinctrl_ephy3_led: ephy3_led-pins {
  181. function = "ephy3_led";
  182. pins = "gpio9";
  183. };
  184. pinctrl_robosw_led_data: robosw_led_data-pins {
  185. function = "robosw_led_data";
  186. pins = "gpio10";
  187. };
  188. pinctrl_robosw_led_clk: robosw_led_clk-pins {
  189. function = "robosw_led_clk";
  190. pins = "gpio11";
  191. };
  192. pinctrl_robosw_led0: robosw_led0-pins {
  193. function = "robosw_led0";
  194. pins = "gpio12";
  195. };
  196. pinctrl_robosw_led1: robosw_led1-pins {
  197. function = "robosw_led1";
  198. pins = "gpio13";
  199. };
  200. pinctrl_usb_device_led: usb_device_led-pins {
  201. function = "usb_device_led";
  202. pins = "gpio14";
  203. };
  204. pinctrl_pci: pci-pins {
  205. pinctrl_pci_req1: pci_req1-pins {
  206. function = "pci_req1";
  207. pins = "gpio16";
  208. };
  209. pinctrl_pci_gnt1: pci_gnt1-pins {
  210. function = "pci_gnt1";
  211. pins = "gpio17";
  212. };
  213. pinctrl_pci_intb: pci_intb-pins {
  214. function = "pci_intb";
  215. pins = "gpio18";
  216. };
  217. pinctrl_pci_req0: pci_req0-pins {
  218. function = "pci_req0";
  219. pins = "gpio19";
  220. };
  221. pinctrl_pci_gnt0: pci_gnt0-pins {
  222. function = "pci_gnt0";
  223. pins = "gpio20";
  224. };
  225. };
  226. pinctrl_pcmcia: pcmcia-pins {
  227. pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
  228. function = "pcmcia_cd1";
  229. pins = "gpio22";
  230. };
  231. pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
  232. function = "pcmcia_cd2";
  233. pins = "gpio23";
  234. };
  235. pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
  236. function = "pcmcia_vs1";
  237. pins = "gpio24";
  238. };
  239. pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
  240. function = "pcmcia_vs2";
  241. pins = "gpio25";
  242. };
  243. };
  244. pinctrl_ebi_cs2: ebi_cs2-pins {
  245. function = "ebi_cs2";
  246. pins = "gpio26";
  247. };
  248. pinctrl_ebi_cs3: ebi_cs3-pins {
  249. function = "ebi_cs3";
  250. pins = "gpio27";
  251. };
  252. pinctrl_spi_cs2: spi_cs2-pins {
  253. function = "spi_cs2";
  254. pins = "gpio28";
  255. };
  256. pinctrl_spi_cs3: spi_cs3-pins {
  257. function = "spi_cs3";
  258. pins = "gpio29";
  259. };
  260. pinctrl_spi_cs4: spi_cs4-pins {
  261. function = "spi_cs4";
  262. pins = "gpio30";
  263. };
  264. pinctrl_spi_cs5: spi_cs5-pins {
  265. function = "spi_cs5";
  266. pins = "gpio31";
  267. };
  268. pinctrl_uart1: uart1-pins {
  269. function = "uart1";
  270. pins = "uart1_grp";
  271. };
  272. };
  273. };
  274. leds: led-controller@100000d0 {
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. compatible = "brcm,bcm6358-leds";
  278. reg = <0x100000d0 0x8>;
  279. status = "disabled";
  280. };
  281. uart0: serial@10000100 {
  282. compatible = "brcm,bcm6345-uart";
  283. reg = <0x10000100 0x18>;
  284. interrupt-parent = <&periph_intc>;
  285. interrupts = <BCM6368_IRQ_UART0>;
  286. clocks = <&periph_osc>;
  287. clock-names = "periph";
  288. status = "disabled";
  289. };
  290. uart1: serial@10000120 {
  291. compatible = "brcm,bcm6345-uart";
  292. reg = <0x10000120 0x18>;
  293. interrupt-parent = <&periph_intc>;
  294. interrupts = <BCM6368_IRQ_UART1>;
  295. clocks = <&periph_osc>;
  296. clock-names = "periph";
  297. status = "disabled";
  298. };
  299. nflash: nand@10000200 {
  300. #address-cells = <1>;
  301. #size-cells = <0>;
  302. compatible = "brcm,nand-bcm6368",
  303. "brcm,brcmnand-v2.1",
  304. "brcm,brcmnand";
  305. reg = <0x10000200 0x180>,
  306. <0x10000600 0x200>,
  307. <0x10000070 0x10>;
  308. reg-names = "nand",
  309. "nand-cache",
  310. "nand-int-base";
  311. interrupt-parent = <&periph_intc>;
  312. interrupts = <BCM6368_IRQ_NAND>;
  313. clocks = <&periph_clk BCM6368_CLK_NAND>;
  314. clock-names = "nand";
  315. status = "disabled";
  316. };
  317. lsspi: spi@10000800 {
  318. #address-cells = <1>;
  319. #size-cells = <0>;
  320. compatible = "brcm,bcm6358-spi";
  321. reg = <0x10000800 0x70c>;
  322. interrupt-parent = <&periph_intc>;
  323. interrupts = <BCM6368_IRQ_SPI>;
  324. clocks = <&periph_clk BCM6368_CLK_SPI>;
  325. clock-names = "spi";
  326. resets = <&periph_rst BCM6368_RST_SPI>;
  327. status = "disabled";
  328. };
  329. pci: pci@10001000 {
  330. compatible = "brcm,bcm6348-pci";
  331. reg = <0x10001000 0x200>;
  332. #address-cells = <3>;
  333. #size-cells = <2>;
  334. device_type = "pci";
  335. bus-range = <0x00 0x01>;
  336. ranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>,
  337. <0x1000000 0 0x08000000 0x08000000 0 0x0010000>;
  338. linux,pci-probe-only = <1>;
  339. interrupt-parent = <&periph_intc>;
  340. interrupts = <BCM6368_IRQ_MPI>;
  341. resets = <&periph_rst BCM6368_RST_MPI>;
  342. reset-names = "pci";
  343. pinctrl-names = "default";
  344. pinctrl-0 = <&pinctrl_pci>;
  345. brcm,remap;
  346. status = "disabled";
  347. };
  348. ehci: usb@10001500 {
  349. compatible = "brcm,bcm6368-ehci", "generic-ehci";
  350. reg = <0x10001500 0x100>;
  351. big-endian;
  352. spurious-oc;
  353. interrupt-parent = <&periph_intc>;
  354. interrupts = <BCM6368_IRQ_EHCI>;
  355. phys = <&usbh 0>;
  356. phy-names = "usb";
  357. status = "disabled";
  358. };
  359. ohci: usb@10001600 {
  360. compatible = "brcm,bcm6368-ohci", "generic-ohci";
  361. reg = <0x10001600 0x100>;
  362. big-endian;
  363. no-big-frame-no;
  364. interrupt-parent = <&periph_intc>;
  365. interrupts = <BCM6368_IRQ_OHCI>;
  366. phys = <&usbh 0>;
  367. phy-names = "usb";
  368. status = "disabled";
  369. };
  370. usbh: usb-phy@10001700 {
  371. compatible = "brcm,bcm6368-usbh-phy";
  372. reg = <0x10001700 0x38>;
  373. #phy-cells = <1>;
  374. clocks = <&periph_clk BCM6368_CLK_USBH>;
  375. clock-names = "usbh";
  376. resets = <&periph_rst BCM6368_RST_USBH>;
  377. status = "disabled";
  378. };
  379. random: rng@10004180 {
  380. compatible = "brcm,bcm6368-rng";
  381. reg = <0x10004180 0x14>;
  382. clocks = <&periph_clk BCM6368_CLK_IPSEC>;
  383. clock-names = "ipsec";
  384. resets = <&periph_rst BCM6368_RST_IPSEC>;
  385. };
  386. ethernet: ethernet@10006800 {
  387. compatible = "brcm,bcm6368-enetsw";
  388. reg = <0x10006800 0x80>,
  389. <0x10006a00 0x80>,
  390. <0x10006c00 0x80>;
  391. reg-names = "dma",
  392. "dma-channels",
  393. "dma-sram";
  394. interrupt-parent = <&periph_intc>;
  395. interrupts = <BCM6368_IRQ_ENETSW_RX_DMA0>,
  396. <BCM6368_IRQ_ENETSW_TX_DMA0>;
  397. interrupt-names = "rx",
  398. "tx";
  399. clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>,
  400. <&periph_clk BCM6368_CLK_SWPKT_SAR>,
  401. <&periph_clk BCM6368_CLK_ROBOSW>;
  402. resets = <&periph_rst BCM6368_RST_SWITCH>,
  403. <&periph_rst BCM6368_RST_EPHY>;
  404. dma-rx = <0>;
  405. dma-tx = <1>;
  406. status = "disabled";
  407. };
  408. switch0: switch@10f00000 {
  409. #address-cells = <1>;
  410. #size-cells = <0>;
  411. compatible = "brcm,bcm6368-switch";
  412. reg = <0x10f00000 0x8000>;
  413. big-endian;
  414. ports {
  415. #address-cells = <1>;
  416. #size-cells = <0>;
  417. port@8 {
  418. reg = <8>;
  419. phy-mode = "internal";
  420. ethernet = <&ethernet>;
  421. fixed-link {
  422. speed = <1000>;
  423. full-duplex;
  424. };
  425. };
  426. };
  427. };
  428. mdio: mdio@10f000b0 {
  429. #address-cells = <1>;
  430. #size-cells = <0>;
  431. compatible = "brcm,bcm6368-mdio-mux";
  432. reg = <0x10f000b0 0x8>;
  433. mdio_int: mdio@0 {
  434. #address-cells = <1>;
  435. #size-cells = <0>;
  436. reg = <0>;
  437. phy1: ethernet-phy@1 {
  438. compatible = "ethernet-phy-ieee802.3-c22";
  439. reg = <1>;
  440. };
  441. phy2: ethernet-phy@2 {
  442. compatible = "ethernet-phy-ieee802.3-c22";
  443. reg = <2>;
  444. };
  445. phy3: ethernet-phy@3 {
  446. compatible = "ethernet-phy-ieee802.3-c22";
  447. reg = <3>;
  448. };
  449. phy4: ethernet-phy@4 {
  450. compatible = "ethernet-phy-ieee802.3-c22";
  451. reg = <4>;
  452. };
  453. };
  454. mdio_ext: mdio@1 {
  455. #address-cells = <1>;
  456. #size-cells = <0>;
  457. reg = <1>;
  458. };
  459. };
  460. };
  461. pflash: nor@18000000 {
  462. #address-cells = <1>;
  463. #size-cells = <1>;
  464. compatible = "cfi-flash";
  465. reg = <0x18000000 0x2000000>;
  466. bank-width = <2>;
  467. status = "disabled";
  468. };
  469. };