550-ath9k-of.patch 4.2 KB

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  1. --- a/drivers/net/wireless/ath/ath9k/init.c
  2. +++ b/drivers/net/wireless/ath/ath9k/init.c
  3. @@ -28,6 +28,11 @@
  4. #include "ath9k.h"
  5. +#ifdef CONFIG_ATH79
  6. +#include <asm/mach-ath79/ath79.h>
  7. +#include <asm/mach-ath79/ar71xx_regs.h>
  8. +#endif
  9. +
  10. struct ath9k_eeprom_ctx {
  11. struct completion complete;
  12. struct ath_hw *ah;
  13. @@ -242,6 +247,81 @@ static unsigned int ath9k_reg_rmw(void *
  14. return val;
  15. }
  16. +#ifdef CONFIG_ATH79
  17. +#define QCA955X_DDR_CTL_CONFIG 0x108
  18. +#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23)
  19. +
  20. +static int ar913x_wmac_reset(void)
  21. +{
  22. + ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
  23. + mdelay(10);
  24. +
  25. + ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
  26. + mdelay(10);
  27. +
  28. + return 0;
  29. +}
  30. +
  31. +static int ar933x_wmac_reset(void)
  32. +{
  33. + int retries = 20;
  34. +
  35. + ath79_device_reset_set(AR933X_RESET_WMAC);
  36. + ath79_device_reset_clear(AR933X_RESET_WMAC);
  37. +
  38. + while (1) {
  39. + u32 bootstrap;
  40. +
  41. + bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  42. + if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
  43. + return 0;
  44. +
  45. + if (retries-- == 0)
  46. + break;
  47. +
  48. + udelay(10000);
  49. + }
  50. +
  51. + pr_err("ar933x: WMAC reset timed out");
  52. + return -ETIMEDOUT;
  53. +}
  54. +
  55. +static int qca955x_wmac_reset(void)
  56. +{
  57. + int i;
  58. +
  59. + /* Try to wait for WMAC DDR activity to stop */
  60. + for (i = 0; i < 10; i++) {
  61. + if (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) &
  62. + QCA955X_DDR_CTL_CONFIG_ACT_WMAC))
  63. + break;
  64. +
  65. + udelay(10);
  66. + }
  67. +
  68. + ath79_device_reset_set(QCA955X_RESET_RTC);
  69. + udelay(10);
  70. + ath79_device_reset_clear(QCA955X_RESET_RTC);
  71. + udelay(10);
  72. +
  73. + return 0;
  74. +}
  75. +
  76. +
  77. +static int ar9330_get_soc_revision(void)
  78. +{
  79. + if (ath79_soc_rev == 1)
  80. + return ath79_soc_rev;
  81. +
  82. + return 0;
  83. +}
  84. +
  85. +static int ath79_get_soc_revision(void)
  86. +{
  87. + return ath79_soc_rev;
  88. +}
  89. +#endif
  90. +
  91. /**************************/
  92. /* Initialization */
  93. /**************************/
  94. @@ -626,6 +706,7 @@ static int ath9k_of_init(struct ath_soft
  95. struct ath_common *common = ath9k_hw_common(ah);
  96. enum ath_bus_type bus_type = common->bus_ops->ath_bus_type;
  97. char eeprom_name[100];
  98. + u32 mask;
  99. int ret;
  100. if (!of_device_is_available(np))
  101. @@ -633,6 +714,43 @@ static int ath9k_of_init(struct ath_soft
  102. ath_dbg(common, CONFIG, "parsing configuration from OF node\n");
  103. + if (!of_property_read_u32(np, "qca,gpio-mask", &mask))
  104. + ah->caps.gpio_mask = mask;
  105. +
  106. + if (of_property_read_bool(np, "qca,tx-gain-buffalo"))
  107. + ah->config.tx_gain_buffalo = true;
  108. +
  109. +#ifdef CONFIG_ATH79
  110. + if (ah->hw_version.devid == AR5416_AR9100_DEVID) {
  111. + ah->external_reset = ar913x_wmac_reset;
  112. + } else if (ah->hw_version.devid == AR9300_DEVID_AR9330) {
  113. + ah->get_mac_revision = ar9330_get_soc_revision;
  114. + u32 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  115. + ah->is_clk_25mhz = !(t & AR933X_BOOTSTRAP_REF_CLK_40);
  116. + ah->external_reset = ar933x_wmac_reset;
  117. + } else if (ah->hw_version.devid == AR9300_DEVID_AR9340) {
  118. + ah->get_mac_revision = ath79_get_soc_revision;
  119. + u32 t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
  120. + ah->is_clk_25mhz = !(t & AR934X_BOOTSTRAP_REF_CLK_40);
  121. + } else if (ah->hw_version.devid == AR9300_DEVID_AR953X) {
  122. + ah->get_mac_revision = ath79_get_soc_revision;
  123. + /*
  124. + * QCA953x only supports 25MHz refclk.
  125. + * Some vendors have an invalid bootstrap option
  126. + * set, which would break the WMAC here.
  127. + */
  128. + ah->is_clk_25mhz = true;
  129. + } else if (ah->hw_version.devid == AR9300_DEVID_QCA955X) {
  130. + u32 t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
  131. + ah->is_clk_25mhz = !(t & QCA955X_BOOTSTRAP_REF_CLK_40);
  132. + ah->external_reset = qca955x_wmac_reset;
  133. + } else if (ah->hw_version.devid == AR9300_DEVID_QCA956X) {
  134. + ah->get_mac_revision = ath79_get_soc_revision;
  135. + u32 t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
  136. + ah->is_clk_25mhz = !(t & QCA956X_BOOTSTRAP_REF_CLK_40);
  137. + }
  138. +#endif
  139. +
  140. if (of_property_read_bool(np, "qca,no-eeprom")) {
  141. /* ath9k-eeprom-<bus>-<id>.bin */
  142. scnprintf(eeprom_name, sizeof(eeprom_name),
  143. @@ -651,6 +769,17 @@ static int ath9k_of_init(struct ath_soft
  144. if (ret == -EPROBE_DEFER)
  145. return ret;
  146. + np = of_get_child_by_name(np, "led");
  147. + if (np && of_device_is_available(np)) {
  148. + u32 led_pin;
  149. +
  150. + if (!of_property_read_u32(np, "led-sources", &led_pin))
  151. + ah->led_pin = led_pin;
  152. +
  153. + ah->config.led_active_high = !of_property_read_bool(np, "led-active-low");
  154. + of_node_put(np);
  155. + }
  156. +
  157. return 0;
  158. }