bcm6318.dtsi 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /dts-v1/;
  3. #include <dt-bindings/clock/bcm6318-clock.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/interrupt-controller/bcm6318-interrupt-controller.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/leds/common.h>
  9. #include <dt-bindings/reset/bcm6318-reset.h>
  10. #include <dt-bindings/soc/bcm6318-pm.h>
  11. / {
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. compatible = "brcm,bcm6318";
  15. aliases {
  16. pinctrl = &pinctrl;
  17. serial0 = &uart0;
  18. spi1 = &hsspi;
  19. };
  20. chosen {
  21. bootargs = "earlycon";
  22. stdout-path = "serial0:115200n8";
  23. };
  24. clocks {
  25. periph_osc: periph-osc {
  26. compatible = "fixed-clock";
  27. #clock-cells = <0>;
  28. clock-frequency = <50000000>;
  29. clock-output-names = "periph";
  30. };
  31. hsspi_osc: hsspi-osc {
  32. compatible = "fixed-clock";
  33. #clock-cells = <0>;
  34. clock-frequency = <250000000>;
  35. clock-output-names = "hsspi_osc";
  36. };
  37. };
  38. cpus {
  39. #address-cells = <1>;
  40. #size-cells = <0>;
  41. mips-hpt-frequency = <166500000>;
  42. cpu@0 {
  43. compatible = "brcm,bmips3300", "mips,mips4Kc";
  44. device_type = "cpu";
  45. reg = <0>;
  46. };
  47. };
  48. cpu_intc: interrupt-controller {
  49. #address-cells = <0>;
  50. compatible = "mti,cpu-interrupt-controller";
  51. interrupt-controller;
  52. #interrupt-cells = <1>;
  53. };
  54. memory@0 {
  55. device_type = "memory";
  56. reg = <0 0>;
  57. };
  58. ubus {
  59. #address-cells = <1>;
  60. #size-cells = <1>;
  61. compatible = "simple-bus";
  62. ranges;
  63. periph_clk: clock-controller@10000004 {
  64. compatible = "brcm,bcm6318-clocks";
  65. reg = <0x10000004 0x4>;
  66. #clock-cells = <1>;
  67. };
  68. ubus_clk: clock-controller@10000008 {
  69. compatible = "brcm,bcm6318-ubus-clocks";
  70. reg = <0x10000008 0x4>;
  71. #clock-cells = <1>;
  72. };
  73. periph_rst: reset-controller@10000010 {
  74. compatible = "brcm,bcm6345-reset";
  75. reg = <0x10000010 0x4>;
  76. #reset-cells = <1>;
  77. };
  78. ext_intc: interrupt-controller@10000018 {
  79. #address-cells = <1>;
  80. compatible = "brcm,bcm6318-ext-intc";
  81. reg = <0x10000018 0x4>;
  82. interrupt-controller;
  83. #interrupt-cells = <2>;
  84. interrupt-parent = <&periph_intc>;
  85. interrupts = <BCM6318_IRQ_EXT0>,
  86. <BCM6318_IRQ_EXT1>,
  87. <BCM6318_IRQ_EXT2>,
  88. <BCM6318_IRQ_EXT3>;
  89. };
  90. periph_intc: interrupt-controller@10000020 {
  91. #address-cells = <1>;
  92. compatible = "brcm,bcm6345-l1-intc";
  93. reg = <0x10000020 0x20>;
  94. interrupt-controller;
  95. #interrupt-cells = <1>;
  96. interrupt-parent = <&cpu_intc>;
  97. interrupts = <2>, <3>;
  98. };
  99. wdt: watchdog@10000068 {
  100. compatible = "brcm,bcm7038-wdt";
  101. reg = <0x10000068 0xc>;
  102. clocks = <&periph_osc>;
  103. timeout-sec = <30>;
  104. };
  105. pll_cntl: syscon@10000074 {
  106. compatible = "syscon", "simple-mfd";
  107. reg = <0x10000074 0x4>;
  108. native-endian;
  109. syscon-reboot {
  110. compatible = "syscon-reboot";
  111. offset = <0>;
  112. mask = <0x1>;
  113. };
  114. };
  115. gpio_cntl: syscon@10000080 {
  116. #address-cells = <1>;
  117. #size-cells = <1>;
  118. compatible = "brcm,bcm6318-gpio-sysctl",
  119. "syscon", "simple-mfd";
  120. reg = <0x10000080 0x80>;
  121. ranges = <0 0x10000080 0x80>;
  122. native-endian;
  123. gpio: gpio@0 {
  124. compatible = "brcm,bcm6318-gpio";
  125. reg-names = "dirout", "dat";
  126. reg = <0x0 0x8>, <0x8 0x8>;
  127. gpio-controller;
  128. gpio-ranges = <&pinctrl 0 0 50>;
  129. #gpio-cells = <2>;
  130. };
  131. pinctrl: pinctrl@18 {
  132. compatible = "brcm,bcm6318-pinctrl";
  133. reg = <0x18 0x10>, <0x54 0x18>;
  134. pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
  135. function = "ephy0_spd_led";
  136. pins = "gpio0";
  137. };
  138. pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
  139. function = "ephy1_spd_led";
  140. pins = "gpio1";
  141. };
  142. pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
  143. function = "ephy2_spd_led";
  144. pins = "gpio2";
  145. };
  146. pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
  147. function = "ephy3_spd_led";
  148. pins = "gpio3";
  149. };
  150. pinctrl_ephy0_act_led: ephy0_act_led-pins {
  151. function = "ephy0_act_led";
  152. pins = "gpio4";
  153. };
  154. pinctrl_ephy1_act_led: ephy1_act_led-pins {
  155. function = "ephy1_act_led";
  156. pins = "gpio5";
  157. };
  158. pinctrl_ephy2_act_led: ephy2_act_led-pins {
  159. function = "ephy2_act_led";
  160. pins = "gpio6";
  161. };
  162. pinctrl_ephy3_act_led: ephy3_act_led-pins {
  163. function = "ephy3_act_led";
  164. pins = "gpio7";
  165. };
  166. pinctrl_serial_led: serial_led-pins {
  167. pinctrl_serial_led_data: serial_led_data-pins {
  168. function = "serial_led_data";
  169. pins = "gpio6";
  170. };
  171. pinctrl_serial_led_clk: serial_led_clk-pins {
  172. function = "serial_led_clk";
  173. pins = "gpio7";
  174. };
  175. };
  176. pinctrl_inet_act_led: inet_act_led-pins {
  177. function = "inet_act_led";
  178. pins = "gpio8";
  179. };
  180. pinctrl_inet_fail_led: inet_fail_led-pins {
  181. function = "inet_fail_led";
  182. pins = "gpio9";
  183. };
  184. pinctrl_dsl_led: dsl_led-pins {
  185. function = "dsl_led";
  186. pins = "gpio10";
  187. };
  188. pinctrl_post_fail_led: post_fail_led-pins {
  189. function = "post_fail_led";
  190. pins = "gpio11";
  191. };
  192. pinctrl_wlan_wps_led: wlan_wps_led-pins {
  193. function = "wlan_wps_led";
  194. pins = "gpio12";
  195. };
  196. pinctrl_usb_pwron: usb_pwron-pins {
  197. function = "usb_pwron";
  198. pins = "gpio13";
  199. };
  200. pinctrl_usb_device_led: usb_device_led-pins {
  201. function = "usb_device_led";
  202. pins = "gpio13";
  203. };
  204. pinctrl_usb_active: usb_active-pins {
  205. function = "usb_active";
  206. pins = "gpio40";
  207. };
  208. };
  209. ephy_rst: reset-controller@3c {
  210. compatible = "brcm,bcm6345-reset";
  211. reg = <0x3c 0x4>;
  212. #reset-cells = <1>;
  213. };
  214. };
  215. uart0: serial@10000100 {
  216. compatible = "brcm,bcm6345-uart";
  217. reg = <0x10000100 0x18>;
  218. interrupt-parent = <&periph_intc>;
  219. interrupts = <BCM6318_IRQ_UART0>;
  220. clocks = <&periph_osc>;
  221. clock-names = "periph";
  222. status = "disabled";
  223. };
  224. leds: led-controller@10000200 {
  225. #address-cells = <1>;
  226. #size-cells = <0>;
  227. compatible = "brcm,bcm6328-leds";
  228. reg = <0x10000200 0x24>;
  229. status = "disabled";
  230. };
  231. periph_pwr: power-controller@100008e8 {
  232. compatible = "brcm,bcm6318-power-controller";
  233. reg = <0x100008e8 0x4>;
  234. #power-domain-cells = <1>;
  235. };
  236. hsspi: spi@10003000 {
  237. #address-cells = <1>;
  238. #size-cells = <0>;
  239. compatible = "brcm,bcm6328-hsspi";
  240. reg = <0x10003000 0x600>;
  241. interrupt-parent = <&periph_intc>;
  242. interrupts = <BCM6318_IRQ_HSSPI>;
  243. clocks = <&periph_clk BCM6318_CLK_HSSPI>,
  244. <&hsspi_osc>;
  245. clock-names = "hsspi",
  246. "pll";
  247. resets = <&periph_rst BCM6318_RST_SPI>;
  248. status = "disabled";
  249. };
  250. ehci: usb@10005000 {
  251. compatible = "brcm,bcm6318-ehci", "generic-ehci";
  252. reg = <0x10005000 0x100>;
  253. big-endian;
  254. spurious-oc;
  255. interrupt-parent = <&periph_intc>;
  256. interrupts = <BCM6318_IRQ_EHCI>;
  257. phys = <&usbh 0>;
  258. phy-names = "usb";
  259. status = "disabled";
  260. };
  261. ohci: usb@10005100 {
  262. compatible = "brcm,bcm6318-ohci", "generic-ohci";
  263. reg = <0x10005100 0x100>;
  264. big-endian;
  265. no-big-frame-no;
  266. interrupt-parent = <&periph_intc>;
  267. interrupts = <BCM6318_IRQ_OHCI>;
  268. phys = <&usbh 0>;
  269. phy-names = "usb";
  270. status = "disabled";
  271. };
  272. usbh: usb-phy@10005200 {
  273. compatible = "brcm,bcm6318-usbh-phy";
  274. reg = <0x10005200 0x38>;
  275. #phy-cells = <1>;
  276. clocks = <&periph_clk BCM6318_CLK_USBD>,
  277. <&ubus_clk BCM6318_UCLK_USB>;
  278. clock-names = "usbh",
  279. "usb_ref";
  280. power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_USB>;
  281. resets = <&periph_rst BCM6318_RST_USBH>;
  282. status = "disabled";
  283. };
  284. pcie: pcie@10010000 {
  285. compatible = "brcm,bcm6318-pcie";
  286. reg = <0x10010000 0x10000>;
  287. #address-cells = <3>;
  288. #size-cells = <2>;
  289. device_type = "pci";
  290. bus-range = <0x00 0x01>;
  291. ranges = <0x2000000 0 0x10200000 0x10200000 0 0x100000>;
  292. linux,pci-probe-only = <1>;
  293. interrupt-parent = <&periph_intc>;
  294. interrupts = <BCM6318_IRQ_PCIE_RC>;
  295. clocks = <&periph_clk BCM6318_CLK_PCIE>,
  296. <&periph_clk BCM6318_CLK_PCIE25>,
  297. <&ubus_clk BCM6318_UCLK_PCIE>;
  298. clock-names = "pcie",
  299. "pcie25",
  300. "pcie-ubus";
  301. resets = <&periph_rst BCM6318_RST_PCIE>,
  302. <&periph_rst BCM6318_RST_PCIE_EXT>,
  303. <&periph_rst BCM6318_RST_PCIE_CORE>,
  304. <&periph_rst BCM6318_RST_PCIE_HARD>;
  305. reset-names = "pcie",
  306. "pcie-ext",
  307. "pcie-core",
  308. "pcie-hard";
  309. power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_PCIE>;
  310. status = "disabled";
  311. };
  312. switch0: switch@10080000 {
  313. #address-cells = <1>;
  314. #size-cells = <0>;
  315. compatible = "brcm,bcm6318-switch";
  316. reg = <0x10080000 0x8000>;
  317. big-endian;
  318. brcm,gpio-ctrl = <&gpio_cntl>;
  319. ports {
  320. #address-cells = <1>;
  321. #size-cells = <0>;
  322. port@8 {
  323. reg = <8>;
  324. phy-mode = "internal";
  325. ethernet = <&ethernet>;
  326. fixed-link {
  327. speed = <1000>;
  328. full-duplex;
  329. };
  330. };
  331. };
  332. };
  333. mdio: mdio@100800b0 {
  334. #address-cells = <1>;
  335. #size-cells = <0>;
  336. compatible = "brcm,bcm6368-mdio-mux";
  337. reg = <0x100800b0 0x8>;
  338. mdio_int: mdio@0 {
  339. #address-cells = <1>;
  340. #size-cells = <0>;
  341. reg = <0>;
  342. phy1: ethernet-phy@1 {
  343. compatible = "ethernet-phy-ieee802.3-c22";
  344. reg = <1>;
  345. resets = <&ephy_rst 0>;
  346. reset-names = "phy";
  347. reset-assert-us = <2000>;
  348. reset-deassert-us = <2000>;
  349. };
  350. phy2: ethernet-phy@2 {
  351. compatible = "ethernet-phy-ieee802.3-c22";
  352. reg = <2>;
  353. resets = <&ephy_rst 1>;
  354. reset-names = "phy";
  355. reset-assert-us = <2000>;
  356. reset-deassert-us = <2000>;
  357. };
  358. phy3: ethernet-phy@3 {
  359. compatible = "ethernet-phy-ieee802.3-c22";
  360. reg = <3>;
  361. resets = <&ephy_rst 2>;
  362. reset-names = "phy";
  363. reset-assert-us = <2000>;
  364. reset-deassert-us = <2000>;
  365. };
  366. phy4: ethernet-phy@4 {
  367. compatible = "ethernet-phy-ieee802.3-c22";
  368. reg = <4>;
  369. resets = <&ephy_rst 3>;
  370. reset-names = "phy";
  371. reset-assert-us = <2000>;
  372. reset-deassert-us = <2000>;
  373. };
  374. };
  375. mdio_ext: mdio@1 {
  376. #address-cells = <1>;
  377. #size-cells = <0>;
  378. reg = <1>;
  379. };
  380. };
  381. ethernet: ethernet@10088000 {
  382. compatible = "brcm,bcm6318-enetsw";
  383. reg = <0x10088000 0x80>,
  384. <0x10088200 0x80>,
  385. <0x10088400 0x80>;
  386. reg-names = "dma",
  387. "dma-channels",
  388. "dma-sram";
  389. interrupt-parent = <&periph_intc>;
  390. interrupts = <BCM6318_IRQ_ENETSW_RX_DMA0>,
  391. <BCM6318_IRQ_ENETSW_TX_DMA0>;
  392. interrupt-names = "rx",
  393. "tx";
  394. clocks = <&periph_clk BCM6318_CLK_ROBOSW250>,
  395. <&periph_clk BCM6318_CLK_ROBOSW025>,
  396. <&ubus_clk BCM6318_UCLK_ROBOSW>;
  397. resets = <&periph_rst BCM6318_RST_ENETSW>,
  398. <&periph_rst BCM6318_RST_EPHY>;
  399. power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_EPHY0>,
  400. <&periph_pwr BCM6318_POWER_DOMAIN_EPHY1>,
  401. <&periph_pwr BCM6318_POWER_DOMAIN_EPHY2>,
  402. <&periph_pwr BCM6318_POWER_DOMAIN_EPHY3>;
  403. dma-rx = <0>;
  404. dma-tx = <1>;
  405. status = "disabled";
  406. };
  407. };
  408. };