bcm6328.dtsi 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /dts-v1/;
  3. #include <dt-bindings/clock/bcm6328-clock.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/interrupt-controller/bcm6328-interrupt-controller.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/leds/common.h>
  9. #include <dt-bindings/reset/bcm6328-reset.h>
  10. #include <dt-bindings/soc/bcm6328-pm.h>
  11. / {
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. compatible = "brcm,bcm6328";
  15. aliases {
  16. nflash = &nflash;
  17. pinctrl = &pinctrl;
  18. serial0 = &uart0;
  19. serial1 = &uart1;
  20. spi1 = &hsspi;
  21. };
  22. chosen {
  23. bootargs = "earlycon";
  24. stdout-path = "serial0:115200n8";
  25. };
  26. clocks {
  27. periph_osc: periph-osc {
  28. compatible = "fixed-clock";
  29. #clock-cells = <0>;
  30. clock-frequency = <50000000>;
  31. clock-output-names = "periph";
  32. };
  33. hsspi_osc: hsspi-osc {
  34. compatible = "fixed-clock";
  35. #clock-cells = <0>;
  36. clock-frequency = <133333333>;
  37. clock-output-names = "hsspi_osc";
  38. };
  39. };
  40. cpus {
  41. #address-cells = <1>;
  42. #size-cells = <0>;
  43. mips-hpt-frequency = <160000000>;
  44. cpu@0 {
  45. compatible = "brcm,bmips4350", "mips,mips4Kc";
  46. device_type = "cpu";
  47. reg = <0>;
  48. };
  49. cpu@1 {
  50. compatible = "brcm,bmips4350", "mips,mips4Kc";
  51. device_type = "cpu";
  52. reg = <1>;
  53. };
  54. };
  55. cpu_intc: interrupt-controller {
  56. #address-cells = <0>;
  57. compatible = "mti,cpu-interrupt-controller";
  58. interrupt-controller;
  59. #interrupt-cells = <1>;
  60. };
  61. memory@0 {
  62. device_type = "memory";
  63. reg = <0 0>;
  64. };
  65. ubus {
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. compatible = "simple-bus";
  69. ranges;
  70. periph_clk: clock-controller@10000004 {
  71. compatible = "brcm,bcm6328-clocks";
  72. reg = <0x10000004 0x4>;
  73. #clock-cells = <1>;
  74. };
  75. periph_rst: reset-controller@10000010 {
  76. compatible = "brcm,bcm6345-reset";
  77. reg = <0x10000010 0x4>;
  78. #reset-cells = <1>;
  79. };
  80. ext_intc: interrupt-controller@10000018 {
  81. #address-cells = <1>;
  82. compatible = "brcm,bcm6345-ext-intc";
  83. reg = <0x10000018 0x4>;
  84. interrupt-controller;
  85. #interrupt-cells = <2>;
  86. interrupt-parent = <&periph_intc>;
  87. interrupts = <BCM6328_IRQ_EXTO>,
  88. <BCM6328_IRQ_EXT1>,
  89. <BCM6328_IRQ_EXT2>,
  90. <BCM6328_IRQ_EXT3>;
  91. };
  92. periph_intc: interrupt-controller@10000020 {
  93. #address-cells = <1>;
  94. compatible = "brcm,bcm6345-l1-intc";
  95. reg = <0x10000020 0x10>,
  96. <0x10000030 0x10>;
  97. interrupt-controller;
  98. #interrupt-cells = <1>;
  99. interrupt-parent = <&cpu_intc>;
  100. interrupts = <2>, <3>;
  101. };
  102. wdt: watchdog@1000005c {
  103. compatible = "brcm,bcm7038-wdt";
  104. reg = <0x1000005c 0xc>;
  105. clocks = <&periph_osc>;
  106. timeout-sec = <30>;
  107. };
  108. pll_cntl: syscon@10000068 {
  109. compatible = "syscon", "simple-mfd";
  110. reg = <0x10000068 0x4>;
  111. native-endian;
  112. syscon-reboot {
  113. compatible = "syscon-reboot";
  114. offset = <0>;
  115. mask = <0x1>;
  116. };
  117. };
  118. gpio_cntl: syscon@10000080 {
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. compatible = "brcm,bcm6328-gpio-sysctl",
  122. "syscon", "simple-mfd";
  123. reg = <0x10000080 0x80>;
  124. ranges = <0 0x10000080 0x80>;
  125. native-endian;
  126. gpio: gpio@0 {
  127. compatible = "brcm,bcm6328-gpio";
  128. reg-names = "dirout", "dat";
  129. reg = <0x0 0x8>, <0x8 0x8>;
  130. gpio-controller;
  131. gpio-ranges = <&pinctrl 0 0 32>;
  132. #gpio-cells = <2>;
  133. };
  134. pinctrl: pinctrl@18 {
  135. compatible = "brcm,bcm6328-pinctrl";
  136. reg = <0x18 0x10>;
  137. pinctrl_serial_led: serial_led-pins {
  138. pinctrl_serial_led_data: serial_led_data-pins {
  139. function = "serial_led_data";
  140. pins = "gpio6";
  141. };
  142. pinctrl_serial_led_clk: serial_led_clk-pins {
  143. function = "serial_led_clk";
  144. pins = "gpio7";
  145. };
  146. };
  147. pinctrl_inet_act_led: inet_act_led-pins {
  148. function = "inet_act_led";
  149. pins = "gpio11";
  150. };
  151. pinctrl_pcie_clkreq: pcie_clkreq-pins {
  152. function = "pcie_clkreq";
  153. pins = "gpio16";
  154. };
  155. pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
  156. function = "led";
  157. pins = "gpio17";
  158. };
  159. pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
  160. function = "led";
  161. pins = "gpio18";
  162. };
  163. pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
  164. function = "led";
  165. pins = "gpio19";
  166. };
  167. pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
  168. function = "led";
  169. pins = "gpio20";
  170. };
  171. pinctrl_ephy0_act_led: ephy0_act_led-pins {
  172. function = "ephy0_act_led";
  173. pins = "gpio25";
  174. };
  175. pinctrl_ephy1_act_led: ephy1_act_led-pins {
  176. function = "ephy1_act_led";
  177. pins = "gpio26";
  178. };
  179. pinctrl_ephy2_act_led: ephy2_act_led-pins {
  180. function = "ephy2_act_led";
  181. pins = "gpio27";
  182. };
  183. pinctrl_ephy3_act_led: ephy3_act_led-pins {
  184. function = "ephy3_act_led";
  185. pins = "gpio28";
  186. };
  187. pinctrl_hsspi_cs1: hsspi_cs1-pins {
  188. function = "hsspi_cs1";
  189. pins = "hsspi_cs1";
  190. };
  191. pinctrl_usb_port1_device: usb_port1_device-pins {
  192. function = "usb_device_port";
  193. pins = "usb_port1";
  194. };
  195. pinctrl_usb_port1_host: usb_port1_host-pins {
  196. function = "usb_host_port";
  197. pins = "usb_port1";
  198. };
  199. };
  200. ephy_rst: reset-controller@3c {
  201. compatible = "brcm,bcm6345-reset";
  202. reg = <0x3c 0x4>;
  203. #reset-cells = <1>;
  204. };
  205. };
  206. uart0: serial@10000100 {
  207. compatible = "brcm,bcm6345-uart";
  208. reg = <0x10000100 0x18>;
  209. interrupt-parent = <&periph_intc>;
  210. interrupts = <BCM6328_IRQ_UART0>;
  211. clocks = <&periph_osc>;
  212. clock-names = "periph";
  213. status = "disabled";
  214. };
  215. uart1: serial@10000120 {
  216. compatible = "brcm,bcm6345-uart";
  217. reg = <0x10000120 0x18>;
  218. interrupt-parent = <&periph_intc>;
  219. interrupts = <BCM6328_IRQ_UART1>;
  220. clocks = <&periph_osc>;
  221. clock-names = "periph";
  222. status = "disabled";
  223. };
  224. nflash: nand@10000200 {
  225. #address-cells = <1>;
  226. #size-cells = <0>;
  227. compatible = "brcm,nand-bcm6368",
  228. "brcm,brcmnand-v2.2",
  229. "brcm,brcmnand";
  230. reg = <0x10000200 0x180>,
  231. <0x10000400 0x200>,
  232. <0x10000070 0x10>;
  233. reg-names = "nand",
  234. "nand-cache",
  235. "nand-int-base";
  236. interrupt-parent = <&periph_intc>;
  237. interrupts = <BCM6328_IRQ_NAND>;
  238. status = "disabled";
  239. };
  240. leds: led-controller@10000800 {
  241. #address-cells = <1>;
  242. #size-cells = <0>;
  243. compatible = "brcm,bcm6328-leds";
  244. reg = <0x10000800 0x24>;
  245. status = "disabled";
  246. };
  247. hsspi: spi@10001000 {
  248. #address-cells = <1>;
  249. #size-cells = <0>;
  250. compatible = "brcm,bcm6328-hsspi";
  251. reg = <0x10001000 0x600>;
  252. interrupt-parent = <&periph_intc>;
  253. interrupts = <BCM6328_IRQ_HSSPI>;
  254. clocks = <&periph_clk BCM6328_CLK_HSSPI>,
  255. <&hsspi_osc>;
  256. clock-names = "hsspi",
  257. "pll";
  258. resets = <&periph_rst BCM6328_RST_SPI>;
  259. status = "disabled";
  260. };
  261. serdes_cntl: syscon@10001800 {
  262. compatible = "syscon";
  263. reg = <0x10001800 0x4>;
  264. native-endian;
  265. };
  266. periph_pwr: power-controller@10001848 {
  267. compatible = "brcm,bcm6328-power-controller";
  268. reg = <0x10001848 0x4>;
  269. #power-domain-cells = <1>;
  270. };
  271. ehci: usb@10002500 {
  272. compatible = "brcm,bcm6328-ehci", "generic-ehci";
  273. reg = <0x10002500 0x100>;
  274. big-endian;
  275. spurious-oc;
  276. interrupt-parent = <&periph_intc>;
  277. interrupts = <BCM6328_IRQ_EHCI>;
  278. phys = <&usbh 0>;
  279. phy-names = "usb";
  280. status = "disabled";
  281. };
  282. ohci: usb@10002600 {
  283. compatible = "brcm,bcm6328-ohci", "generic-ohci";
  284. reg = <0x10002600 0x100>;
  285. big-endian;
  286. no-big-frame-no;
  287. interrupt-parent = <&periph_intc>;
  288. interrupts = <BCM6328_IRQ_OHCI>;
  289. phys = <&usbh 0>;
  290. phy-names = "usb";
  291. status = "disabled";
  292. };
  293. usbh: usb-phy@10002700 {
  294. compatible = "brcm,bcm6328-usbh-phy";
  295. reg = <0x10002700 0x38>;
  296. #phy-cells = <1>;
  297. clocks = <&periph_clk BCM6328_CLK_USBH>;
  298. clock-names = "usbh";
  299. power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_USBH>;
  300. resets = <&periph_rst BCM6328_RST_USBH>;
  301. status = "disabled";
  302. };
  303. ethernet: ethernet@1000d800 {
  304. compatible = "brcm,bcm6328-enetsw";
  305. reg = <0x1000d800 0x80>,
  306. <0x1000da00 0x80>,
  307. <0x1000dc00 0x80>;
  308. reg-names = "dma",
  309. "dma-channels",
  310. "dma-sram";
  311. interrupt-parent = <&periph_intc>;
  312. interrupts = <BCM6328_IRQ_ENETSW_RX_DMA0>,
  313. <BCM6328_IRQ_ENETSW_TX_DMA0>;
  314. interrupt-names = "rx",
  315. "tx";
  316. clocks = <&periph_clk BCM6328_CLK_ROBOSW>;
  317. resets = <&periph_rst BCM6328_RST_ENETSW>,
  318. <&periph_rst BCM6328_RST_EPHY>;
  319. power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_ROBOSW>,
  320. <&periph_pwr BCM6328_POWER_DOMAIN_EPHY>;
  321. dma-rx = <0>;
  322. dma-tx = <1>;
  323. status = "disabled";
  324. };
  325. switch0: switch@10e00000 {
  326. #address-cells = <1>;
  327. #size-cells = <0>;
  328. compatible = "brcm,bcm6328-switch";
  329. reg = <0x10e00000 0x8000>;
  330. big-endian;
  331. brcm,gpio-ctrl = <&gpio_cntl>;
  332. ports {
  333. #address-cells = <1>;
  334. #size-cells = <0>;
  335. port@8 {
  336. reg = <8>;
  337. phy-mode = "internal";
  338. ethernet = <&ethernet>;
  339. fixed-link {
  340. speed = <1000>;
  341. full-duplex;
  342. };
  343. };
  344. };
  345. };
  346. mdio: mdio@10e000b0 {
  347. #address-cells = <1>;
  348. #size-cells = <0>;
  349. compatible = "brcm,bcm6368-mdio-mux";
  350. reg = <0x10e000b0 0x8>;
  351. mdio_int: mdio@0 {
  352. #address-cells = <1>;
  353. #size-cells = <0>;
  354. reg = <0>;
  355. phy1: ethernet-phy@1 {
  356. compatible = "ethernet-phy-ieee802.3-c22";
  357. reg = <1>;
  358. resets = <&ephy_rst 0>;
  359. reset-names = "phy";
  360. reset-assert-us = <2000>;
  361. reset-deassert-us = <2000>;
  362. };
  363. phy2: ethernet-phy@2 {
  364. compatible = "ethernet-phy-ieee802.3-c22";
  365. reg = <2>;
  366. resets = <&ephy_rst 1>;
  367. reset-names = "phy";
  368. reset-assert-us = <2000>;
  369. reset-deassert-us = <2000>;
  370. };
  371. phy3: ethernet-phy@3 {
  372. compatible = "ethernet-phy-ieee802.3-c22";
  373. reg = <3>;
  374. resets = <&ephy_rst 2>;
  375. reset-names = "phy";
  376. reset-assert-us = <2000>;
  377. reset-deassert-us = <2000>;
  378. };
  379. phy4: ethernet-phy@4 {
  380. compatible = "ethernet-phy-ieee802.3-c22";
  381. reg = <4>;
  382. resets = <&ephy_rst 3>;
  383. reset-names = "phy";
  384. reset-assert-us = <2000>;
  385. reset-deassert-us = <2000>;
  386. };
  387. };
  388. mdio_ext: mdio@1 {
  389. #address-cells = <1>;
  390. #size-cells = <0>;
  391. reg = <1>;
  392. };
  393. };
  394. pcie: pcie@10e40000 {
  395. compatible = "brcm,bcm6328-pcie";
  396. reg = <0x10e40000 0x10000>;
  397. #address-cells = <3>;
  398. #size-cells = <2>;
  399. device_type = "pci";
  400. bus-range = <0x00 0x01>;
  401. ranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;
  402. linux,pci-probe-only = <1>;
  403. interrupt-parent = <&periph_intc>;
  404. interrupts = <BCM6328_IRQ_PCIE_RC>;
  405. clocks = <&periph_clk BCM6328_CLK_PCIE>;
  406. clock-names = "pcie";
  407. resets = <&periph_rst BCM6328_RST_PCIE>,
  408. <&periph_rst BCM6328_RST_PCIE_EXT>,
  409. <&periph_rst BCM6328_RST_PCIE_CORE>,
  410. <&periph_rst BCM6328_RST_PCIE_HARD>;
  411. reset-names = "pcie",
  412. "pcie-ext",
  413. "pcie-core",
  414. "pcie-hard";
  415. power-domains = <&periph_pwr BCM6328_POWER_DOMAIN_PCIE>;
  416. brcm,serdes = <&serdes_cntl>;
  417. status = "disabled";
  418. };
  419. };
  420. };