bcm6362.dtsi 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /dts-v1/;
  3. #include <dt-bindings/clock/bcm6362-clock.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/leds/common.h>
  9. #include <dt-bindings/reset/bcm6362-reset.h>
  10. #include <dt-bindings/soc/bcm6362-pm.h>
  11. / {
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. compatible = "brcm,bcm6362";
  15. aliases {
  16. nflash = &nflash;
  17. pinctrl = &pinctrl;
  18. serial0 = &uart0;
  19. serial1 = &uart1;
  20. spi0 = &lsspi;
  21. spi1 = &hsspi;
  22. };
  23. chosen {
  24. bootargs = "earlycon";
  25. stdout-path = "serial0:115200n8";
  26. };
  27. clocks {
  28. periph_osc: periph-osc {
  29. compatible = "fixed-clock";
  30. #clock-cells = <0>;
  31. clock-frequency = <50000000>;
  32. clock-output-names = "periph";
  33. };
  34. hsspi_osc: hsspi-osc {
  35. compatible = "fixed-clock";
  36. #clock-cells = <0>;
  37. clock-frequency = <400000000>;
  38. clock-output-names = "hsspi_osc";
  39. };
  40. };
  41. cpus {
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. mips-hpt-frequency = <200000000>;
  45. cpu@0 {
  46. compatible = "brcm,bmips4350", "mips,mips4Kc";
  47. device_type = "cpu";
  48. reg = <0>;
  49. };
  50. cpu@1 {
  51. compatible = "brcm,bmips4350", "mips,mips4Kc";
  52. device_type = "cpu";
  53. reg = <1>;
  54. };
  55. };
  56. cpu_intc: interrupt-controller {
  57. #address-cells = <0>;
  58. compatible = "mti,cpu-interrupt-controller";
  59. interrupt-controller;
  60. #interrupt-cells = <1>;
  61. };
  62. memory@0 {
  63. device_type = "memory";
  64. reg = <0 0>;
  65. };
  66. ubus {
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. compatible = "simple-bus";
  70. ranges;
  71. periph_clk: clock-controller@10000004 {
  72. compatible = "brcm,bcm6362-clocks";
  73. reg = <0x10000004 0x4>;
  74. #clock-cells = <1>;
  75. };
  76. pll_cntl: syscon@10000008 {
  77. compatible = "syscon", "simple-mfd";
  78. reg = <0x10000008 0x4>;
  79. native-endian;
  80. syscon-reboot {
  81. compatible = "syscon-reboot";
  82. offset = <0x0>;
  83. mask = <0x1>;
  84. };
  85. };
  86. periph_rst: reset-controller@10000010 {
  87. compatible = "brcm,bcm6345-reset";
  88. reg = <0x10000010 0x4>;
  89. #reset-cells = <1>;
  90. };
  91. ext_intc: interrupt-controller@10000018 {
  92. #address-cells = <1>;
  93. compatible = "brcm,bcm6345-ext-intc";
  94. reg = <0x10000018 0x4>;
  95. interrupt-controller;
  96. #interrupt-cells = <2>;
  97. interrupt-parent = <&periph_intc>;
  98. interrupts = <BCM6362_IRQ_EXT0>,
  99. <BCM6362_IRQ_EXT1>,
  100. <BCM6362_IRQ_EXT2>,
  101. <BCM6362_IRQ_EXT3>;
  102. };
  103. periph_intc: interrupt-controller@10000020 {
  104. #address-cells = <1>;
  105. compatible = "brcm,bcm6345-l1-intc";
  106. reg = <0x10000020 0x10>,
  107. <0x10000030 0x10>;
  108. interrupt-controller;
  109. #interrupt-cells = <1>;
  110. interrupt-parent = <&cpu_intc>;
  111. interrupts = <2>, <3>;
  112. };
  113. wdt: watchdog@1000005c {
  114. compatible = "brcm,bcm7038-wdt";
  115. reg = <0x1000005c 0xc>;
  116. clocks = <&periph_osc>;
  117. timeout-sec = <30>;
  118. };
  119. gpio_cntl: syscon@10000080 {
  120. #address-cells = <1>;
  121. #size-cells = <1>;
  122. compatible = "brcm,bcm6362-gpio-sysctl",
  123. "syscon", "simple-mfd";
  124. reg = <0x10000080 0x80>;
  125. ranges = <0 0x10000080 0x80>;
  126. native-endian;
  127. gpio: gpio@0 {
  128. compatible = "brcm,bcm6362-gpio";
  129. reg-names = "dirout", "dat";
  130. reg = <0x0 0x8>, <0x8 0x8>;
  131. gpio-controller;
  132. gpio-ranges = <&pinctrl 0 0 48>;
  133. #gpio-cells = <2>;
  134. };
  135. pinctrl: pinctrl@18 {
  136. compatible = "brcm,bcm6362-pinctrl";
  137. reg = <0x18 0x10>, <0x38 0x4>;
  138. pinctrl_usb_device_led: usb_device_led-pins {
  139. function = "usb_device_led";
  140. pins = "gpio0";
  141. };
  142. pinctrl_sys_irq: sys_irq-pins {
  143. function = "sys_irq";
  144. pins = "gpio1";
  145. };
  146. pinctrl_serial_led: serial_led-pins {
  147. pinctrl_serial_led_clk: serial_led_clk-pins {
  148. function = "serial_led_clk";
  149. pins = "gpio2";
  150. };
  151. pinctrl_serial_led_data: serial_led_data-pins {
  152. function = "serial_led_data";
  153. pins = "gpio3";
  154. };
  155. };
  156. pinctrl_robosw_led_data: robosw_led_data-pins {
  157. function = "robosw_led_data";
  158. pins = "gpio4";
  159. };
  160. pinctrl_robosw_led_clk: robosw_led_clk-pins {
  161. function = "robosw_led_clk";
  162. pins = "gpio5";
  163. };
  164. pinctrl_robosw_led0: robosw_led0-pins {
  165. function = "robosw_led0";
  166. pins = "gpio6";
  167. };
  168. pinctrl_robosw_led1: robosw_led1-pins {
  169. function = "robosw_led1";
  170. pins = "gpio7";
  171. };
  172. pinctrl_inet_led: inet_led-pins {
  173. function = "inet_led";
  174. pins = "gpio8";
  175. };
  176. pinctrl_spi_cs2: spi_cs2-pins {
  177. function = "spi_cs2";
  178. pins = "gpio9";
  179. };
  180. pinctrl_spi_cs3: spi_cs3-pins {
  181. function = "spi_cs3";
  182. pins = "gpio10";
  183. };
  184. pinctrl_ntr_pulse: ntr_pulse-pins {
  185. function = "ntr_pulse";
  186. pins = "gpio11";
  187. };
  188. pinctrl_uart1_scts: uart1_scts-pins {
  189. function = "uart1_scts";
  190. pins = "gpio12";
  191. };
  192. pinctrl_uart1_srts: uart1_srts-pins {
  193. function = "uart1_srts";
  194. pins = "gpio13";
  195. };
  196. pinctrl_uart1: uart1-pins {
  197. pinctrl_uart1_sdin: uart1_sdin-pins {
  198. function = "uart1_sdin";
  199. pins = "gpio14";
  200. };
  201. pinctrl_uart1_sdout: uart1_sdout-pins {
  202. function = "uart1_sdout";
  203. pins = "gpio15";
  204. };
  205. };
  206. pinctrl_adsl_spi: adsl_spi-pins {
  207. pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
  208. function = "adsl_spi_miso";
  209. pins = "gpio16";
  210. };
  211. pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
  212. function = "adsl_spi_mosi";
  213. pins = "gpio17";
  214. };
  215. pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
  216. function = "adsl_spi_clk";
  217. pins = "gpio18";
  218. };
  219. pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
  220. function = "adsl_spi_cs";
  221. pins = "gpio19";
  222. };
  223. };
  224. pinctrl_ephy0_led: ephy0_led-pins {
  225. function = "ephy0_led";
  226. pins = "gpio20";
  227. };
  228. pinctrl_ephy1_led: ephy1_led-pins {
  229. function = "ephy1_led";
  230. pins = "gpio21";
  231. };
  232. pinctrl_ephy2_led: ephy2_led-pins {
  233. function = "ephy2_led";
  234. pins = "gpio22";
  235. };
  236. pinctrl_ephy3_led: ephy3_led-pins {
  237. function = "ephy3_led";
  238. pins = "gpio23";
  239. };
  240. pinctrl_ext_irq0: ext_irq0-pins {
  241. function = "ext_irq0";
  242. pins = "gpio24";
  243. };
  244. pinctrl_ext_irq1: ext_irq1-pins {
  245. function = "ext_irq1";
  246. pins = "gpio25";
  247. };
  248. pinctrl_ext_irq2: ext_irq2-pins {
  249. function = "ext_irq2";
  250. pins = "gpio26";
  251. };
  252. pinctrl_ext_irq3: ext_irq3-pins {
  253. function = "ext_irq3";
  254. pins = "gpio27";
  255. };
  256. pinctrl_nand: nand-pins {
  257. function = "nand";
  258. pins = "nand_grp";
  259. };
  260. };
  261. ephy_rst: reset-controller@3c {
  262. compatible = "brcm,bcm6345-reset";
  263. reg = <0x3c 0x4>;
  264. #reset-cells = <1>;
  265. };
  266. };
  267. uart0: serial@10000100 {
  268. compatible = "brcm,bcm6345-uart";
  269. reg = <0x10000100 0x18>;
  270. interrupt-parent = <&periph_intc>;
  271. interrupts = <BCM6362_IRQ_UART0>;
  272. clocks = <&periph_osc>;
  273. clock-names = "periph";
  274. status = "disabled";
  275. };
  276. uart1: serial@10000120 {
  277. compatible = "brcm,bcm6345-uart";
  278. reg = <0x10000120 0x18>;
  279. interrupt-parent = <&periph_intc>;
  280. interrupts = <BCM6362_IRQ_UART1>;
  281. clocks = <&periph_osc>;
  282. clock-names = "periph";
  283. status = "disabled";
  284. };
  285. nflash: nand@10000200 {
  286. #address-cells = <1>;
  287. #size-cells = <0>;
  288. compatible = "brcm,nand-bcm6368",
  289. "brcm,brcmnand-v2.2",
  290. "brcm,brcmnand";
  291. reg = <0x10000200 0x180>,
  292. <0x10000600 0x200>,
  293. <0x10000070 0x10>;
  294. reg-names = "nand",
  295. "nand-cache",
  296. "nand-int-base";
  297. interrupt-parent = <&periph_intc>;
  298. interrupts = <BCM6362_IRQ_NAND>;
  299. clocks = <&periph_clk BCM6362_CLK_NAND>;
  300. clock-names = "nand";
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&pinctrl_nand>;
  303. status = "disabled";
  304. };
  305. lsspi: spi@10000800 {
  306. #address-cells = <1>;
  307. #size-cells = <0>;
  308. compatible = "brcm,bcm6358-spi";
  309. reg = <0x10000800 0x70c>;
  310. interrupt-parent = <&periph_intc>;
  311. interrupts = <BCM6362_IRQ_LSSPI>;
  312. clocks = <&periph_clk BCM6362_CLK_SPI>;
  313. clock-names = "spi";
  314. resets = <&periph_rst BCM6362_RST_SPI>;
  315. status = "disabled";
  316. };
  317. hsspi: spi@10001000 {
  318. #address-cells = <1>;
  319. #size-cells = <0>;
  320. compatible = "brcm,bcm6328-hsspi";
  321. reg = <0x10001000 0x600>;
  322. interrupt-parent = <&periph_intc>;
  323. interrupts = <BCM6362_IRQ_HSSPI>;
  324. clocks = <&periph_clk BCM6362_CLK_HSSPI>,
  325. <&hsspi_osc>;
  326. clock-names = "hsspi",
  327. "pll";
  328. resets = <&periph_rst BCM6362_RST_SPI>;
  329. status = "disabled";
  330. };
  331. serdes_cntl: syscon@10001804 {
  332. compatible = "syscon";
  333. reg = <0x10001804 0x4>;
  334. native-endian;
  335. };
  336. periph_pwr: power-controller@10001848 {
  337. compatible = "brcm,bcm6362-power-controller";
  338. reg = <0x10001848 0x4>;
  339. #power-domain-cells = <1>;
  340. };
  341. leds: led-controller@10001900 {
  342. #address-cells = <1>;
  343. #size-cells = <0>;
  344. compatible = "brcm,bcm6328-leds";
  345. reg = <0x10001900 0x24>;
  346. status = "disabled";
  347. };
  348. ehci: usb@10002500 {
  349. compatible = "brcm,bcm6362-ehci", "generic-ehci";
  350. reg = <0x10002500 0x100>;
  351. big-endian;
  352. spurious-oc;
  353. interrupt-parent = <&periph_intc>;
  354. interrupts = <BCM6362_IRQ_EHCI>;
  355. phys = <&usbh 0>;
  356. phy-names = "usb";
  357. status = "disabled";
  358. };
  359. ohci: usb@10002600 {
  360. compatible = "brcm,bcm6362-ohci", "generic-ohci";
  361. reg = <0x10002600 0x100>;
  362. big-endian;
  363. no-big-frame-no;
  364. interrupt-parent = <&periph_intc>;
  365. interrupts = <BCM6362_IRQ_OHCI>;
  366. phys = <&usbh 0>;
  367. phy-names = "usb";
  368. status = "disabled";
  369. };
  370. usbh: usb-phy@10002700 {
  371. compatible = "brcm,bcm6362-usbh-phy";
  372. reg = <0x10002700 0x38>;
  373. #phy-cells = <1>;
  374. clocks = <&periph_clk BCM6362_CLK_USBH>;
  375. clock-names = "usbh";
  376. power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>;
  377. resets = <&periph_rst BCM6362_RST_USBH>;
  378. status = "disabled";
  379. };
  380. random: rng@10002880 {
  381. compatible = "brcm,bcm6368-rng";
  382. reg = <0x10002880 0x14>;
  383. clocks = <&periph_clk BCM6362_CLK_IPSEC>;
  384. clock-names = "ipsec";
  385. resets = <&periph_rst BCM6362_RST_IPSEC>;
  386. power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_IPSEC>;
  387. };
  388. ethernet: ethernet@1000d800 {
  389. compatible = "brcm,bcm6362-enetsw";
  390. reg = <0x1000d800 0x80>,
  391. <0x1000da00 0x80>,
  392. <0x1000dc00 0x80>;
  393. reg-names = "dma",
  394. "dma-channels",
  395. "dma-sram";
  396. interrupt-parent = <&periph_intc>;
  397. interrupts = <BCM6362_IRQ_ENETSW_RX_DMA0>;
  398. interrupt-names = "rx";
  399. clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,
  400. <&periph_clk BCM6362_CLK_SWPKT_SAR>,
  401. <&periph_clk BCM6362_CLK_ROBOSW>;
  402. resets = <&periph_rst BCM6362_RST_ENETSW>,
  403. <&periph_rst BCM6362_RST_EPHY>;
  404. power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_ROBOSW>,
  405. <&periph_pwr BCM6362_POWER_DOMAIN_GMII_PADS>;
  406. dma-rx = <0>;
  407. dma-tx = <1>;
  408. status = "disabled";
  409. };
  410. switch0: switch@10e00000 {
  411. #address-cells = <1>;
  412. #size-cells = <0>;
  413. compatible = "brcm,bcm6362-switch";
  414. reg = <0x10e00000 0x8000>;
  415. big-endian;
  416. brcm,gpio-ctrl = <&gpio_cntl>;
  417. ports {
  418. #address-cells = <1>;
  419. #size-cells = <0>;
  420. port@8 {
  421. reg = <8>;
  422. phy-mode = "internal";
  423. ethernet = <&ethernet>;
  424. fixed-link {
  425. speed = <1000>;
  426. full-duplex;
  427. };
  428. };
  429. };
  430. };
  431. mdio: mdio@10e000b0 {
  432. #address-cells = <1>;
  433. #size-cells = <0>;
  434. compatible = "brcm,bcm6368-mdio-mux";
  435. reg = <0x10e000b0 0x8>;
  436. mdio_int: mdio@0 {
  437. #address-cells = <1>;
  438. #size-cells = <0>;
  439. reg = <0>;
  440. phy1: ethernet-phy@1 {
  441. compatible = "ethernet-phy-ieee802.3-c22";
  442. reg = <1>;
  443. resets = <&ephy_rst 0>;
  444. reset-names = "phy";
  445. reset-assert-us = <2000>;
  446. reset-deassert-us = <2000>;
  447. };
  448. phy2: ethernet-phy@2 {
  449. compatible = "ethernet-phy-ieee802.3-c22";
  450. reg = <2>;
  451. resets = <&ephy_rst 1>;
  452. reset-names = "phy";
  453. reset-assert-us = <2000>;
  454. reset-deassert-us = <2000>;
  455. };
  456. phy3: ethernet-phy@3 {
  457. compatible = "ethernet-phy-ieee802.3-c22";
  458. reg = <3>;
  459. resets = <&ephy_rst 2>;
  460. reset-names = "phy";
  461. reset-assert-us = <2000>;
  462. reset-deassert-us = <2000>;
  463. };
  464. phy4: ethernet-phy@4 {
  465. compatible = "ethernet-phy-ieee802.3-c22";
  466. reg = <4>;
  467. resets = <&ephy_rst 3>;
  468. reset-names = "phy";
  469. reset-assert-us = <2000>;
  470. reset-deassert-us = <2000>;
  471. };
  472. };
  473. mdio_ext: mdio@1 {
  474. #address-cells = <1>;
  475. #size-cells = <0>;
  476. reg = <1>;
  477. };
  478. };
  479. pcie: pcie@10e40000 {
  480. compatible = "brcm,bcm6328-pcie";
  481. reg = <0x10e40000 0x10000>;
  482. #address-cells = <3>;
  483. #size-cells = <2>;
  484. device_type = "pci";
  485. bus-range = <0x00 0x01>;
  486. ranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;
  487. linux,pci-probe-only = <1>;
  488. interrupt-parent = <&periph_intc>;
  489. interrupts = <BCM6362_IRQ_PCIE_RC>;
  490. clocks = <&periph_clk BCM6362_CLK_PCIE>;
  491. clock-names = "pcie";
  492. resets = <&periph_rst BCM6362_RST_PCIE>,
  493. <&periph_rst BCM6362_RST_PCIE_EXT>,
  494. <&periph_rst BCM6362_RST_PCIE_CORE>;
  495. reset-names = "pcie",
  496. "pcie-ext",
  497. "pcie-core";
  498. power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_PCIE>;
  499. brcm,serdes = <&serdes_cntl>;
  500. status = "disabled";
  501. };
  502. };
  503. };