ipq5018-ax830.dts 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /*
  3. * Copyright (c) 2025, Shubham Vishwakarma <[email protected]>
  4. */
  5. /dts-v1/;
  6. #include "ipq5018.dtsi"
  7. #include "ipq5018-ess.dtsi"
  8. #include "ipq5018-qcn6122.dtsi"
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/input/input.h>
  11. #include <dt-bindings/leds/common.h>
  12. / {
  13. model = "Yuncore AX830";
  14. compatible = "yuncore,ax830", "qcom,ipq5018";
  15. aliases {
  16. serial0 = &blsp1_uart1;
  17. led-boot = &led_system;
  18. led-failsafe = &led_system;
  19. led-running = &led_system;
  20. led-upgrade = &led_system;
  21. };
  22. chosen {
  23. bootargs-append = " root=/dev/ubiblock0_1 swiotlb=1 coherent_pool=2M";
  24. stdout-path = "serial0:115200n8";
  25. };
  26. keys {
  27. compatible = "gpio-keys";
  28. pinctrl-0 = <&button_pins>;
  29. pinctrl-names = "default";
  30. reset {
  31. label = "reset";
  32. gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
  33. linux,code = <KEY_RESTART>;
  34. };
  35. };
  36. leds {
  37. compatible = "gpio-leds";
  38. led_system: system {
  39. function = LED_FUNCTION_POWER;
  40. color = <LED_COLOR_ID_RED>;
  41. gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
  42. };
  43. wlan2g {
  44. function = LED_FUNCTION_WLAN_2GHZ;
  45. color = <LED_COLOR_ID_GREEN>;
  46. gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
  47. linux,default-trigger = "phy0radio";
  48. };
  49. wlan5g {
  50. function = LED_FUNCTION_WLAN_5GHZ;
  51. color = <LED_COLOR_ID_BLUE>;
  52. gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
  53. linux,default-trigger = "phy1radio";
  54. };
  55. };
  56. gpio-watchdog {
  57. compatible = "linux,wdt-gpio";
  58. gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
  59. hw_algo = "toggle";
  60. hw_margin_ms = <5000>;
  61. always-running;
  62. };
  63. };
  64. &switch {
  65. status = "okay";
  66. switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
  67. qcom,port_phyinfo {
  68. // MAC0 -> GE Phy
  69. port@1 {
  70. port_id = <1>;
  71. mdiobus = <&mdio0>;
  72. phy_address = <7>;
  73. };
  74. // MAC1 -> Uniphy --- SGMII --- QCA8081
  75. port@2 {
  76. port_id = <2>;
  77. mdiobus = <&mdio1>;
  78. phy_address = <28>;
  79. port_mac_sel = "QGMAC_PORT";
  80. };
  81. };
  82. };
  83. // MAC0 -> GE Phy
  84. &dp1 {
  85. status = "okay";
  86. label = "lan";
  87. nvmem-cells = <&hw_mac_addr 0>;
  88. nvmem-cell-names = "mac-address";
  89. phy-mode = "sgmii";
  90. };
  91. // MAC1 ---SGMII---> QCA8081
  92. &dp2 {
  93. status = "okay";
  94. label = "wan";
  95. phy-handle = <&qca8081>;
  96. nvmem-cells = <&hw_mac_addr 1>;
  97. nvmem-cell-names = "mac-address";
  98. };
  99. &mdio0 {
  100. status = "okay";
  101. };
  102. &mdio1 {
  103. status = "okay";
  104. pinctrl-0 = <&mdio1_pins>;
  105. pinctrl-names = "default";
  106. qca8081: ethernet-phy@28 {
  107. compatible = "ethernet-phy-id004d.d101";
  108. reg = <28>;
  109. reset-deassert-us = <10000>;
  110. reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
  111. };
  112. };
  113. &sleep_clk {
  114. clock-frequency = <32000>;
  115. };
  116. &xo_board_clk {
  117. clock-div = <4>;
  118. clock-mult = <1>;
  119. };
  120. &blsp1_uart1 {
  121. status = "okay";
  122. pinctrl-0 = <&serial_0_pins>;
  123. pinctrl-names = "default";
  124. };
  125. &crypto {
  126. status = "okay";
  127. };
  128. &cryptobam {
  129. status = "okay";
  130. };
  131. &prng {
  132. status = "okay";
  133. };
  134. &qfprom {
  135. status = "okay";
  136. };
  137. &qpic_bam {
  138. status = "okay";
  139. };
  140. &blsp1_spi1 {
  141. status = "okay";
  142. flash@0 {
  143. reg = <0>;
  144. compatible = "jedec,spi-nor";
  145. spi-max-frequency = <50000000>;
  146. partitions {
  147. compatible = "fixed-partitions";
  148. #address-cells = <1>;
  149. #size-cells = <1>;
  150. partition@0 {
  151. label = "0:SBL1";
  152. reg = <0x00 0x30000>;
  153. read-only;
  154. };
  155. partition@30000 {
  156. label = "0:MIBIB";
  157. reg = <0x30000 0x10000>;
  158. read-only;
  159. };
  160. partition@40000 {
  161. label = "0:BOOTCONFIG";
  162. reg = <0x40000 0x10000>;
  163. read-only;
  164. };
  165. partition@50000 {
  166. label = "0:BOOTCONFIG1";
  167. reg = <0x50000 0x10000>;
  168. read-only;
  169. };
  170. partition@60000 {
  171. label = "0:QSEE";
  172. reg = <0x60000 0xa0000>;
  173. read-only;
  174. };
  175. partition@100000 {
  176. label = "0:QSEE_1";
  177. reg = <0x100000 0xa0000>;
  178. read-only;
  179. };
  180. partition@1a0000 {
  181. label = "0:DEVCFG";
  182. reg = <0x1a0000 0x10000>;
  183. read-only;
  184. };
  185. partition@1b0000 {
  186. label = "0:DEVCFG_1";
  187. reg = <0x1b0000 0x10000>;
  188. read-only;
  189. };
  190. partition@1c0000 {
  191. label = "0:CDT";
  192. reg = <0x1c0000 0x10000>;
  193. read-only;
  194. };
  195. partition@1d0000 {
  196. label = "0:CDT_1";
  197. reg = <0x1d0000 0x10000>;
  198. read-only;
  199. };
  200. partition@1e0000 {
  201. label = "0:APPSBLENV";
  202. reg = <0x1e0000 0x10000>;
  203. };
  204. partition@1f0000 {
  205. label = "0:APPSBL";
  206. reg = <0x1f0000 0xa0000>;
  207. read-only;
  208. };
  209. partition@290000 {
  210. label = "0:APPSBL_1";
  211. reg = <0x290000 0xa0000>;
  212. read-only;
  213. };
  214. partition@330000 {
  215. label = "0:ART";
  216. reg = <0x330000 0x70000>;
  217. read-only;
  218. nvmem-layout {
  219. compatible = "fixed-layout";
  220. #address-cells = <1>;
  221. #size-cells = <1>;
  222. hw_mac_addr: hw_mac_addr {
  223. #nvmem-cell-cells = <1>;
  224. compatible = "mac-base";
  225. reg = <0x0 0x6>;
  226. };
  227. };
  228. };
  229. };
  230. };
  231. };
  232. &qpic_nand {
  233. pinctrl-0 = <&qpic_pins>;
  234. pinctrl-names = "default";
  235. status = "okay";
  236. nand@0 {
  237. compatible = "spi-nand";
  238. reg = <0>;
  239. nand-ecc-engine = <&qpic_nand>;
  240. nand-bus-width = <8>;
  241. partitions {
  242. compatible = "fixed-partitions";
  243. #address-cells = <1>;
  244. #size-cells = <1>;
  245. partition@0 {
  246. label = "0:TRAINING";
  247. reg = <0x00 0x80000>;
  248. };
  249. partition@80000 {
  250. label = "rootfs_1";
  251. reg = <0x80000 0x3e00000>;
  252. };
  253. partition@3e80000 {
  254. label = "rootfs";
  255. reg = <0x3e80000 0x3e00000>;
  256. };
  257. };
  258. };
  259. };
  260. &tlmm {
  261. button_pins: button-state {
  262. pins = "gpio38";
  263. function = "gpio";
  264. drive-strength = <8>;
  265. bias-pull-up;
  266. };
  267. mdio1_pins: mdio-state {
  268. mdc-pins {
  269. pins = "gpio36";
  270. function = "mdc";
  271. drive-strength = <8>;
  272. bias-pull-up;
  273. };
  274. mdio-pins {
  275. pins = "gpio37";
  276. function = "mdio";
  277. drive-strength = <8>;
  278. bias-pull-up;
  279. };
  280. };
  281. qpic_pins: qpic-state {
  282. clock-pins {
  283. pins = "gpio9";
  284. function = "qspi_clk";
  285. drive-strength = <8>;
  286. bias-disable;
  287. };
  288. cs-pins {
  289. pins = "gpio8";
  290. function = "qspi_cs";
  291. drive-strength = <8>;
  292. bias-disable;
  293. };
  294. data-pins {
  295. pins = "gpio4", "gpio5", "gpio6", "gpio7";
  296. function = "qspi_data";
  297. drive-strength = <8>;
  298. bias-disable;
  299. };
  300. };
  301. serial_0_pins: uart0-state {
  302. pins = "gpio20", "gpio21";
  303. function = "blsp0_uart0";
  304. drive-strength = <8>;
  305. bias-disable;
  306. };
  307. };
  308. &wifi {
  309. status = "okay";
  310. qcom,rproc = <&q6_wcss_pd1>;
  311. qcom,ath11k-calibration-variant = "Yuncore-AX830";
  312. qcom,ath11k-fw-memory-mode = <1>;
  313. qcom,bdf-addr = <0x4c400000>;
  314. };
  315. &wifi1 {
  316. status = "okay";
  317. qcom,rproc = <&q6_wcss_pd3>;
  318. qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
  319. qcom,ath11k-calibration-variant = "Yuncore-AX830";
  320. qcom,ath11k-fw-memory-mode = <1>;
  321. qcom,bdf-addr = <0x4d100000>;
  322. qcom,m3-dump-addr = <0x4df00000>;
  323. };