ipq5018-gl-b3000.dts 5.5 KB

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  1. /dts-v1/;
  2. #include "ipq5018.dtsi"
  3. #include "ipq5018-ess.dtsi"
  4. #include "ipq5018-qcn6122.dtsi"
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/input.h>
  7. #include <dt-bindings/leds/common.h>
  8. / {
  9. model = "GL.iNet GL-B3000";
  10. compatible = "glinet,gl-b3000", "qcom,ipq5018";
  11. aliases {
  12. ethernet1 = &dp2;
  13. label-mac-device = &dp2;
  14. led-boot = &led_system_blue;
  15. led-failsafe = &led_status_white;
  16. led-running = &led_status_white;
  17. led-upgrade = &led_system_blue;
  18. serial0 = &blsp1_uart1;
  19. };
  20. chosen {
  21. bootargs-append = " root=/dev/ubiblock0_1 swiotlb=1 coherent_pool=2M";
  22. stdout-path = "serial0:115200n8";
  23. };
  24. keys {
  25. compatible = "gpio-keys";
  26. pinctrl-0 = <&button_pins>;
  27. pinctrl-names = "default";
  28. button-reset {
  29. label = "reset";
  30. gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
  31. linux,code = <KEY_RESTART>;
  32. };
  33. };
  34. leds {
  35. compatible = "gpio-leds";
  36. pinctrl-0 = <&leds_pins>;
  37. pinctrl-names = "default";
  38. led_system_blue: system-blue {
  39. color = <LED_COLOR_ID_BLUE>;
  40. function = LED_FUNCTION_STATUS;
  41. gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
  42. };
  43. led_status_white: status-white {
  44. color = <LED_COLOR_ID_WHITE>;
  45. function = LED_FUNCTION_STATUS;
  46. gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
  47. };
  48. };
  49. };
  50. &switch {
  51. status = "okay";
  52. switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
  53. qcom,port_phyinfo {
  54. // MAC0 -> GE Phy -> QCA8337 Phy2
  55. port@1 {
  56. port_id = <1>;
  57. mdiobus = <&mdio0>;
  58. phy_address = <7>;
  59. };
  60. // MAC1 ---SGMII---> QCA8337 SerDes
  61. port@2 {
  62. port_id = <2>;
  63. forced-speed = <1000>;
  64. forced-duplex = <1>;
  65. };
  66. };
  67. };
  68. // MAC1 ---SGMII---> QCA8337 SerDes
  69. &dp2 {
  70. status = "okay";
  71. nvmem-cells = <&macaddr_dp2 0>;
  72. nvmem-cell-names = "mac-address";
  73. fixed-link {
  74. speed = <1000>;
  75. full-duplex;
  76. };
  77. };
  78. &mdio0 {
  79. status = "okay";
  80. };
  81. &mdio1 {
  82. status = "okay";
  83. pinctrl-0 = <&mdio1_pins>;
  84. pinctrl-names = "default";
  85. reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
  86. // QCA8337 Phy0 -> WAN
  87. qca8337_0: ethernet-phy@0 {
  88. reg = <0>;
  89. };
  90. // QCA8337 Phy1 -> LAN1
  91. qca8337_1: ethernet-phy@1 {
  92. reg = <1>;
  93. };
  94. // QCA8337 Phy3 -> LAN2
  95. qca8337_2: ethernet-phy@2 {
  96. reg = <2>;
  97. };
  98. // QCA8337 switch
  99. switch0: ethernet-switch@17 {
  100. compatible = "qca,qca8337";
  101. reg = <17>;
  102. #address-cells = <1>;
  103. #size-cells = <0>;
  104. ports {
  105. #address-cells = <1>;
  106. #size-cells = <0>;
  107. switch0cpu: port@0 {
  108. reg = <0>;
  109. label = "cpu";
  110. phy-mode = "sgmii";
  111. ethernet = <&dp2>;
  112. qca,sgmii-enable-pll;
  113. fixed-link {
  114. speed = <1000>;
  115. full-duplex;
  116. };
  117. };
  118. // QCA8337 Phy0 -> WAN
  119. port@1 {
  120. reg = <1>;
  121. label = "wan";
  122. phy-handle = <&qca8337_0>;
  123. };
  124. // QCA8337 Phy1 -> LAN1
  125. port@2 {
  126. reg = <2>;
  127. label = "lan1";
  128. phy-handle = <&qca8337_1>;
  129. nvmem-cells = <&macaddr_dp2 2>;
  130. nvmem-cell-names = "mac-address";
  131. };
  132. // QCA8337 Phy3 -> LAN2
  133. port@3 {
  134. reg = <3>;
  135. label = "lan2";
  136. phy-handle = <&qca8337_2>;
  137. nvmem-cells = <&macaddr_dp2 2>;
  138. nvmem-cell-names = "mac-address";
  139. };
  140. };
  141. };
  142. };
  143. &sleep_clk {
  144. clock-frequency = <32000>;
  145. };
  146. &xo_board_clk {
  147. clock-div = <4>;
  148. clock-mult = <1>;
  149. };
  150. &blsp1_uart1 {
  151. pinctrl-0 = <&serial_0_pins>;
  152. pinctrl-names = "default";
  153. status = "okay";
  154. };
  155. &crypto {
  156. status = "okay";
  157. };
  158. &cryptobam {
  159. status = "okay";
  160. };
  161. &prng {
  162. status = "okay";
  163. };
  164. &qfprom {
  165. status = "okay";
  166. };
  167. &qpic_bam {
  168. status = "okay";
  169. };
  170. &qpic_nand {
  171. pinctrl-0 = <&qpic_pins>;
  172. pinctrl-names = "default";
  173. status = "okay";
  174. nand@0 {
  175. compatible = "spi-nand";
  176. reg = <0>;
  177. nand-ecc-engine = <&qpic_nand>;
  178. nand-bus-width = <8>;
  179. partitions {
  180. compatible = "qcom,smem-part";
  181. partition-0-art {
  182. label = "0:art";
  183. read-only;
  184. nvmem-layout {
  185. compatible = "fixed-layout";
  186. #address-cells = <1>;
  187. #size-cells = <1>;
  188. macaddr_dp2: macaddr@0 {
  189. compatible = "mac-base";
  190. #nvmem-cell-cells = <1>;
  191. reg = <0x6 0x6>;
  192. };
  193. };
  194. };
  195. };
  196. };
  197. };
  198. &tlmm {
  199. mdio1_pins: mdio-state {
  200. mdc-pins {
  201. pins = "gpio36";
  202. function = "mdc";
  203. drive-strength = <8>;
  204. bias-pull-up;
  205. };
  206. mdio-pins {
  207. pins = "gpio37";
  208. function = "mdio";
  209. drive-strength = <8>;
  210. bias-pull-up;
  211. };
  212. };
  213. leds_pins: leds-pins {
  214. pins = "gpio23", "gpio24";
  215. function = "gpio";
  216. drive-strength = <8>;
  217. bias-pull-down;
  218. };
  219. button_pins: button-pins {
  220. pins = "gpio27";
  221. function = "gpio";
  222. drive-strength = <8>;
  223. bias-pull-up;
  224. };
  225. qpic_pins: qpic-state {
  226. clock-pins {
  227. pins = "gpio9";
  228. function = "qspi_clk";
  229. drive-strength = <8>;
  230. bias-disable;
  231. };
  232. cs-pins {
  233. pins = "gpio8";
  234. function = "qspi_cs";
  235. drive-strength = <8>;
  236. bias-disable;
  237. };
  238. data-pins {
  239. pins = "gpio4", "gpio5", "gpio6", "gpio7";
  240. function = "qspi_data";
  241. drive-strength = <8>;
  242. bias-disable;
  243. };
  244. };
  245. serial_0_pins: uart0-state {
  246. pins = "gpio20", "gpio21";
  247. function = "blsp0_uart0";
  248. drive-strength = <8>;
  249. bias-disable;
  250. };
  251. };
  252. &q6v5_wcss {
  253. /* B3000 currently doesn't support passing bootargs */
  254. /*boot-args = < */
  255. /* type: 0x1 PCIE0 */
  256. /* length: 4 */
  257. /* PD id: 3 */
  258. /* reset GPIO: 15 */
  259. /* reserved: 0 0>; */
  260. };
  261. &wifi {
  262. status = "okay";
  263. qcom,rproc = <&q6_wcss_pd1>;
  264. qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
  265. qcom,ath11k-calibration-variant = "GL-iNet-GL-B3000";
  266. qcom,ath11k-fw-memory-mode = <1>;
  267. qcom,bdf-addr = <0x4c400000>;
  268. };
  269. &wifi1 {
  270. status = "okay";
  271. qcom,rproc = <&q6_wcss_pd3>;
  272. qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
  273. qcom,ath11k-calibration-variant = "GL-iNet-GL-B3000";
  274. qcom,ath11k-fw-memory-mode = <1>;
  275. qcom,bdf-addr = <0x4d100000>;
  276. qcom,m3-dump-addr = <0x4df00000>;
  277. };