ipq6010-mango-dvk.dts 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include "ipq6018.dtsi"
  4. #include "ipq6018-cp-cpu.dtsi"
  5. #include "ipq6018-ess.dtsi"
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/input/input.h>
  8. #include <dt-bindings/leds/common.h>
  9. / {
  10. model = "8devices Mango-DVK";
  11. compatible = "8devices,mango-dvk", "qcom,ipq6018";
  12. aliases {
  13. serial0 = &blsp1_uart3;
  14. };
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. keys {
  19. compatible = "gpio-keys";
  20. wps {
  21. label = "wps";
  22. gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
  23. linux,code = <KEY_WPS_BUTTON>;
  24. };
  25. };
  26. leds {
  27. compatible = "gpio-leds";
  28. pinctrl-0 = <&led_pins>;
  29. pinctrl-names = "default";
  30. wlan5g {
  31. color = <LED_COLOR_ID_GREEN>;
  32. function = LED_FUNCTION_WLAN;
  33. function-enumerator = <0>;
  34. gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>;
  35. linux,default-trigger = "phy0radio";
  36. };
  37. wlan2g {
  38. color = <LED_COLOR_ID_GREEN>;
  39. function = LED_FUNCTION_WLAN;
  40. function-enumerator = <1>;
  41. gpios = <&tlmm 67 GPIO_ACTIVE_HIGH>;
  42. linux,default-trigger = "phy1radio";
  43. };
  44. };
  45. };
  46. &tlmm {
  47. mdio_pins: mdio-pins {
  48. mdc {
  49. pins = "gpio64";
  50. function = "mdc";
  51. drive-strength = <8>;
  52. bias-pull-up;
  53. };
  54. mdio {
  55. pins = "gpio65";
  56. function = "mdio";
  57. drive-strength = <8>;
  58. bias-pull-up;
  59. };
  60. };
  61. spi_0_pins: spi-0-pins {
  62. pins = "gpio38", "gpio39", "gpio40", "gpio41";
  63. function = "blsp0_spi";
  64. drive-strength = <8>;
  65. bias-pull-down;
  66. };
  67. led_pins: led_pins {
  68. leds {
  69. pins = "gpio66", "gpio67";
  70. function = "gpio";
  71. drive-strength = <8>;
  72. bias-pull-down;
  73. };
  74. };
  75. sd_pins: sd_pins {
  76. sd_cd {
  77. pins = "gpio62";
  78. function = "gpio";
  79. drive-strength = <8>;
  80. bias-pull-up;
  81. };
  82. };
  83. };
  84. &blsp1_uart3 {
  85. pinctrl-0 = <&serial_3_pins>;
  86. pinctrl-names = "default";
  87. status = "okay";
  88. };
  89. &blsp1_spi1 {
  90. pinctrl-0 = <&spi_0_pins>;
  91. pinctrl-names = "default";
  92. status = "okay";
  93. flash@0 {
  94. reg = <0>;
  95. compatible = "jedec,spi-nor";
  96. spi-max-frequency = <25000000>;
  97. partitions {
  98. compatible = "fixed-partitions";
  99. #address-cells = <1>;
  100. #size-cells = <1>;
  101. partition@0 {
  102. label = "0:SBL1";
  103. reg = <0x00000000 0x000c0000>;
  104. };
  105. partition@c0000 {
  106. label = "0:MIBIB";
  107. reg = <0x000c0000 0x00010000>;
  108. };
  109. partition@d0000 {
  110. label = "0:QSEE";
  111. reg = <0x000d0000 0x001a0000>;
  112. };
  113. partition@270000 {
  114. label = "0:DEVCFG";
  115. reg = <0x00270000 0x00010000>;
  116. };
  117. partition@280000 {
  118. label = "0:RPM";
  119. reg = <0x00280000 0x00020000>;
  120. };
  121. partition@2a0000 {
  122. label = "0:CDT";
  123. reg = <0x002a0000 0x00010000>;
  124. };
  125. partition@2b0000 {
  126. label = "0:APPSBLENV";
  127. reg = <0x002b0000 0x00010000>;
  128. };
  129. partition@2c0000 {
  130. label = "0:APPSBL";
  131. reg = <0x002c0000 0x000a0000>;
  132. };
  133. partition@360000 {
  134. label = "0:ART";
  135. reg = <0x00360000 0x00040000>;
  136. nvmem-layout {
  137. compatible = "fixed-layout";
  138. #address-cells = <1>;
  139. #size-cells = <1>;
  140. macaddr_eth0: macaddr@0 {
  141. reg = <0x0 0x6>;
  142. };
  143. macaddr_eth1: macaddr@6 {
  144. reg = <0x6 0x6>;
  145. };
  146. macaddr_eth2: macaddr@c {
  147. reg = <0xc 0x6>;
  148. };
  149. };
  150. };
  151. partition@3a0000 {
  152. label = "config";
  153. reg = <0x003a0000 0x00040000>;
  154. };
  155. partition@3e0000 {
  156. label = "data";
  157. reg = <0x003e0000 0x00100000>;
  158. };
  159. partition@4e0000 {
  160. label = "firmware";
  161. compatible = "denx,fit";
  162. reg = <0x004e0000 0x1b20000>;
  163. };
  164. };
  165. };
  166. };
  167. &dp3 {
  168. status = "okay";
  169. phy-handle = <&qca8072_1>;
  170. nvmem-cells = <&macaddr_eth1>;
  171. nvmem-cell-names = "mac-address";
  172. label = "lan2";
  173. };
  174. &dp4 {
  175. status = "okay";
  176. phy-handle = <&qca8072_0>;
  177. nvmem-cells = <&macaddr_eth0>;
  178. nvmem-cell-names = "mac-address";
  179. label = "lan1";
  180. };
  181. &dp5 {
  182. status = "okay";
  183. phy-mode = "sgmii";
  184. phy-handle = <&qca8081>;
  185. nvmem-cells = <&macaddr_eth2>;
  186. nvmem-cell-names = "mac-address";
  187. label = "wan";
  188. };
  189. &edma {
  190. status = "okay";
  191. };
  192. &mdio {
  193. status = "okay";
  194. pinctrl-0 = <&mdio_pins>;
  195. pinctrl-names = "default";
  196. reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
  197. reset-delay-us = <10000>;
  198. reset-post-delay-us = <50000>;
  199. ethernet-phy-package@0 {
  200. #address-cells = <1>;
  201. #size-cells = <0>;
  202. compatible = "qcom,qca8075-package";
  203. reg = <0>;
  204. qcom,package-mode = "psgmii";
  205. qca8072_0: ethernet-phy@3 {
  206. compatible = "ethernet-phy-ieee802.3-c22";
  207. reg = <3>;
  208. };
  209. qca8072_1: ethernet-phy@4 {
  210. compatible = "ethernet-phy-ieee802.3-c22";
  211. reg = <4>;
  212. };
  213. };
  214. qca8081: ethernet-phy@24 {
  215. compatible = "ethernet-phy-id004d.d101";
  216. reg = <24>;
  217. reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
  218. reset-assert-us = <10000>;
  219. reset-deassert-us = <50000>;
  220. };
  221. };
  222. &sdhc {
  223. pinctrl-0 = <&sd_pins>;
  224. pinctrl-names = "default";
  225. status = "okay";
  226. bus-width = <4>;
  227. cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
  228. };
  229. &switch {
  230. status = "okay";
  231. switch_lan_bmp = <(ESS_PORT3 | ESS_PORT4)>;
  232. switch_wan_bmp = <ESS_PORT5>;
  233. switch_mac_mode = <MAC_MODE_PSGMII>;
  234. switch_mac_mode1 = <MAC_MODE_SGMII_PLUS>;
  235. port3_pcs_channel = <4>;
  236. qcom,port_phyinfo {
  237. port@3 {
  238. port_id = <3>;
  239. phy_address = <4>;
  240. };
  241. port@4 {
  242. port_id = <4>;
  243. phy_address = <3>;
  244. };
  245. port@5 {
  246. port_id = <5>;
  247. phy_address = <24>;
  248. port_mac_sel = "QGMAC_PORT";
  249. };
  250. };
  251. };
  252. &qpic_bam {
  253. status = "okay";
  254. };
  255. &qpic_nand {
  256. status = "okay";
  257. nand@0 {
  258. reg = <0>;
  259. nand-ecc-strength = <4>;
  260. nand-ecc-step-size = <512>;
  261. nand-bus-width = <8>;
  262. partitions {
  263. compatible = "fixed-partitions";
  264. #address-cells = <1>;
  265. #size-cells = <1>;
  266. partition@0 {
  267. label = "nand_data";
  268. reg = <0x0000000 0x10000000>;
  269. };
  270. };
  271. };
  272. };
  273. &pcie_phy {
  274. status = "okay";
  275. };
  276. &pcie0 {
  277. status = "okay";
  278. perst-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;
  279. };
  280. &wifi {
  281. status = "okay";
  282. qcom,ath11k-calibration-variant = "8devices-Mango";
  283. };
  284. &qusb_phy_1 {
  285. status = "okay";
  286. };
  287. &usb2 {
  288. status = "okay";
  289. };
  290. &qusb_phy_0 {
  291. status = "okay";
  292. };
  293. &ssphy_0 {
  294. status = "okay";
  295. };
  296. &usb3 {
  297. status = "okay";
  298. };