ipq8071-eap102.dts 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /* Copyright (c) 2022, Matthew Hagan <[email protected]> */
  3. /dts-v1/;
  4. #include "ipq8074.dtsi"
  5. #include "ipq8074-ac-cpu.dtsi"
  6. #include "ipq8074-ess.dtsi"
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/input/input.h>
  9. #include <dt-bindings/leds/common.h>
  10. / {
  11. model = "Edgecore EAP102";
  12. compatible = "edgecore,eap102", "qcom,ipq8074";
  13. aliases {
  14. serial0 = &blsp1_uart5;
  15. serial1 = &blsp1_uart3;
  16. led-boot = &led_system_green;
  17. led-failsafe = &led_system_green;
  18. led-running = &led_system_green;
  19. led-upgrade = &led_system_green;
  20. /* Aliases as required by u-boot to patch MAC addresses */
  21. ethernet0 = &dp6;
  22. ethernet1 = &dp5;
  23. label-mac-device = &dp5;
  24. };
  25. chosen {
  26. stdout-path = "serial0:115200n8";
  27. bootargs-append = " root=/dev/ubiblock0_1";
  28. };
  29. keys {
  30. compatible = "gpio-keys";
  31. pinctrl-0 = <&button_pins>;
  32. pinctrl-names = "default";
  33. reset {
  34. label = "reset";
  35. gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
  36. linux,code = <KEY_RESTART>;
  37. };
  38. };
  39. leds {
  40. compatible = "gpio-leds";
  41. led_wanpoe {
  42. label = "green:wanpoe";
  43. gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
  44. };
  45. led_wlan2g {
  46. label = "green:wlan2g";
  47. gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
  48. linux,default-trigger = "phy1radio";
  49. };
  50. led_wlan5g {
  51. label = "green:wlan5g";
  52. gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
  53. linux,default-trigger = "phy0radio";
  54. };
  55. led_system_green: led_system {
  56. function = LED_FUNCTION_POWER;
  57. color = <LED_COLOR_ID_GREEN>;
  58. gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
  59. };
  60. };
  61. };
  62. &tlmm {
  63. mdio_pins: mdio-pins {
  64. mdc {
  65. pins = "gpio68";
  66. function = "mdc";
  67. drive-strength = <8>;
  68. bias-pull-up;
  69. };
  70. mdio {
  71. pins = "gpio69";
  72. function = "mdio";
  73. drive-strength = <8>;
  74. bias-pull-up;
  75. };
  76. };
  77. button_pins: button_pins {
  78. reset_button {
  79. pins = "gpio66";
  80. function = "gpio";
  81. drive-strength = <8>;
  82. bias-pull-up;
  83. };
  84. };
  85. };
  86. &blsp1_spi1 {
  87. status = "okay";
  88. flash@0 {
  89. reg = <0>;
  90. compatible = "jedec,spi-nor";
  91. spi-max-frequency = <50000000>;
  92. partitions {
  93. compatible = "fixed-partitions";
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. partition@0 {
  97. label = "0:sbl1";
  98. reg = <0x0 0x50000>;
  99. read-only;
  100. };
  101. partition@50000 {
  102. label = "0:mibib";
  103. reg = <0x50000 0x10000>;
  104. read-only;
  105. };
  106. partition@60000 {
  107. label = "0:bootconfig";
  108. reg = <0x60000 0x20000>;
  109. read-only;
  110. };
  111. partition@80000 {
  112. label = "0:bootconfig1";
  113. reg = <0x80000 0x20000>;
  114. read-only;
  115. };
  116. partition@a0000 {
  117. label = "0:qsee";
  118. reg = <0xa0000 0x180000>;
  119. read-only;
  120. };
  121. partition@220000 {
  122. label = "0:qsee_1";
  123. reg = <0x220000 0x180000>;
  124. read-only;
  125. };
  126. partition@3a0000 {
  127. label = "0:devcfg";
  128. reg = <0x3a0000 0x10000>;
  129. read-only;
  130. };
  131. partition@3b0000 {
  132. label = "0:devcfg_1";
  133. reg = <0x3b0000 0x10000>;
  134. read-only;
  135. };
  136. partition@3c0000 {
  137. label = "0:apdp";
  138. reg = <0x3c0000 0x10000>;
  139. read-only;
  140. };
  141. partition@3d0000 {
  142. label = "0:apdp_1";
  143. reg = <0x3d0000 0x10000>;
  144. read-only;
  145. };
  146. partition@3e0000 {
  147. label = "0:rpm";
  148. reg = <0x3e0000 0x40000>;
  149. read-only;
  150. };
  151. partition@420000 {
  152. label = "0:rpm_1";
  153. reg = <0x420000 0x40000>;
  154. read-only;
  155. };
  156. partition@460000 {
  157. label = "0:cdt";
  158. reg = <0x460000 0x10000>;
  159. read-only;
  160. };
  161. partition@470000 {
  162. label = "0:cdt_1";
  163. reg = <0x470000 0x10000>;
  164. read-only;
  165. };
  166. partition@480000 {
  167. label = "0:appsblenv";
  168. reg = <0x480000 0x10000>;
  169. };
  170. partition@490000 {
  171. label = "0:appsbl";
  172. reg = <0x490000 0xc0000>;
  173. read-only;
  174. };
  175. partition@550000 {
  176. label = "0:appsbl_1";
  177. reg = <0x530000 0xc0000>;
  178. read-only;
  179. };
  180. partition@610000 {
  181. label = "0:art";
  182. reg = <0x610000 0x40000>;
  183. read-only;
  184. };
  185. partition@650000 {
  186. label = "0:ethphyfw";
  187. reg = <0x650000 0x80000>;
  188. read-only;
  189. };
  190. partition@6d0000 {
  191. label = "0:product_info";
  192. reg = <0x6d0000 0x80000>;
  193. read-only;
  194. };
  195. partition@750000 {
  196. label = "priv_data1";
  197. reg = <0x750000 0x10000>;
  198. read-only;
  199. };
  200. partition@760000 {
  201. label = "priv_data2";
  202. reg = <0x760000 0x10000>;
  203. read-only;
  204. };
  205. };
  206. };
  207. };
  208. &blsp1_uart3 {
  209. status = "okay";
  210. };
  211. &blsp1_uart5 {
  212. status = "okay";
  213. };
  214. &crypto {
  215. status = "okay";
  216. };
  217. &cryptobam {
  218. status = "okay";
  219. };
  220. &prng {
  221. status = "okay";
  222. };
  223. &qpic_bam {
  224. status = "okay";
  225. };
  226. &qusb_phy_0 {
  227. status = "okay";
  228. };
  229. &ssphy_0 {
  230. status = "okay";
  231. };
  232. &usb_0 {
  233. status = "okay";
  234. };
  235. &qpic_nand {
  236. status = "okay";
  237. nand@0 {
  238. reg = <0>;
  239. nand-ecc-strength = <8>;
  240. nand-ecc-step-size = <512>;
  241. nand-bus-width = <8>;
  242. partitions {
  243. compatible = "fixed-partitions";
  244. #address-cells = <1>;
  245. #size-cells = <1>;
  246. partition@0 {
  247. label = "rootfs1";
  248. reg = <0x0000000 0x3400000>;
  249. };
  250. partition@3400000 {
  251. label = "0:wififw";
  252. reg = <0x3400000 0x800000>;
  253. read-only;
  254. };
  255. partition@3c00000 {
  256. label = "rootfs2";
  257. reg = <0x3c00000 0x3400000>;
  258. };
  259. partition@7000000 {
  260. label = "0:wififw_1";
  261. reg = <0x7000000 0x800000>;
  262. read-only;
  263. };
  264. };
  265. };
  266. };
  267. &mdio {
  268. status = "okay";
  269. pinctrl-0 = <&mdio_pins>;
  270. pinctrl-names = "default";
  271. qca8081_24: ethernet-phy@24 {
  272. compatible = "ethernet-phy-id004d.d101";
  273. reg = <24>;
  274. reset-deassert-us = <10000>;
  275. reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
  276. };
  277. qca8081_28: ethernet-phy@28 {
  278. compatible = "ethernet-phy-id004d.d101";
  279. reg = <28>;
  280. reset-deassert-us = <10000>;
  281. reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
  282. };
  283. };
  284. &switch {
  285. status = "okay";
  286. switch_lan_bmp = <ESS_PORT5>; /* lan port bitmap */
  287. switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
  288. switch_mac_mode1 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance1*/
  289. switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance2*/
  290. qcom,port_phyinfo {
  291. port@5 {
  292. port_id = <5>;
  293. phy_address = <24>;
  294. port_mac_sel = "QGMAC_PORT";
  295. };
  296. port@6 {
  297. port_id = <6>;
  298. phy_address = <28>;
  299. port_mac_sel = "QGMAC_PORT";
  300. };
  301. };
  302. };
  303. &edma {
  304. status = "okay";
  305. };
  306. &dp5 {
  307. status = "okay";
  308. phy-mode = "sgmii";
  309. phy-handle = <&qca8081_24>;
  310. label = "lan";
  311. };
  312. &dp6 {
  313. status = "okay";
  314. phy-handle = <&qca8081_28>;
  315. label = "wan";
  316. };
  317. &wifi {
  318. status = "okay";
  319. qcom,ath11k-calibration-variant = "Edgecore-EAP102";
  320. };