rtl839x.dtsi 7.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381
  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "macros.dtsi"
  3. #include <dt-bindings/clock/rtl83xx-clk.h>
  4. /dts-v1/;
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. compatible = "realtek,rtl839x-soc";
  9. osc: oscillator {
  10. compatible = "fixed-clock";
  11. #clock-cells = <0>;
  12. clock-frequency = <25000000>;
  13. };
  14. ccu: clock-controller {
  15. compatible = "realtek,rtl8390-clock";
  16. #clock-cells = <1>;
  17. clocks = <&osc>;
  18. clock-names = "ref_clk";
  19. };
  20. cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. cpu@0 {
  24. compatible = "mips,mips34Kc";
  25. reg = <0>;
  26. clocks = <&ccu CLK_CPU>;
  27. operating-points-v2 = <&cpu_opp_table>;
  28. };
  29. cpu@1 {
  30. compatible = "mips,mips34Kc";
  31. reg = <1>;
  32. clocks = <&ccu CLK_CPU>;
  33. operating-points-v2 = <&cpu_opp_table>;
  34. };
  35. };
  36. cpu_opp_table: opp-table-0 {
  37. compatible = "operating-points-v2";
  38. opp-shared;
  39. opp00 {
  40. opp-hz = /bits/ 64 <425000000>;
  41. };
  42. opp01 {
  43. opp-hz = /bits/ 64 <450000000>;
  44. };
  45. opp02 {
  46. opp-hz = /bits/ 64 <475000000>;
  47. };
  48. opp03 {
  49. opp-hz = /bits/ 64 <500000000>;
  50. };
  51. opp04 {
  52. opp-hz = /bits/ 64 <525000000>;
  53. };
  54. opp05 {
  55. opp-hz = /bits/ 64 <550000000>;
  56. };
  57. opp06 {
  58. opp-hz = /bits/ 64 <575000000>;
  59. };
  60. opp07 {
  61. opp-hz = /bits/ 64 <600000000>;
  62. };
  63. opp08 {
  64. opp-hz = /bits/ 64 <625000000>;
  65. };
  66. opp09 {
  67. opp-hz = /bits/ 64 <650000000>;
  68. };
  69. opp10 {
  70. opp-hz = /bits/ 64 <675000000>;
  71. };
  72. opp11 {
  73. opp-hz = /bits/ 64 <700000000>;
  74. };
  75. opp12 {
  76. opp-hz = /bits/ 64 <725000000>;
  77. };
  78. opp13 {
  79. opp-hz = /bits/ 64 <750000000>;
  80. };
  81. };
  82. aliases {
  83. serial0 = &uart0;
  84. serial1 = &uart1;
  85. };
  86. chosen {
  87. bootargs = "earlycon";
  88. stdout-path = "serial0:115200n8";
  89. };
  90. cpuintc: cpuintc {
  91. compatible = "mti,cpu-interrupt-controller";
  92. #address-cells = <0>;
  93. #interrupt-cells = <1>;
  94. interrupt-controller;
  95. };
  96. soc: soc {
  97. compatible = "simple-bus";
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. ranges = <0x0 0x18000000 0x10000>;
  101. intc: interrupt-controller@3000 {
  102. compatible = "realtek,rtl8390-intc", "realtek,rtl-intc";
  103. reg = <0x3000 0x18>, <0x3018 0x18>;
  104. interrupt-controller;
  105. #interrupt-cells = <2>;
  106. interrupt-parent = <&cpuintc>;
  107. interrupts = <2>, <3>, <4>, <5>, <6>;
  108. };
  109. spi0: spi@1200 {
  110. compatible = "realtek,rtl8380-spi";
  111. reg = <0x1200 0x100>;
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. };
  115. timer0: timer@3100 {
  116. compatible = "realtek,rtl8390-timer", "realtek,otto-timer";
  117. reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
  118. <0x3130 0x10>, <0x3140 0x10>;
  119. interrupt-parent = <&intc>;
  120. interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
  121. clocks = <&ccu CLK_LXB>;
  122. };
  123. uart0: uart@2000 {
  124. compatible = "ns16550a";
  125. reg = <0x2000 0x100>;
  126. clocks = <&ccu CLK_LXB>;
  127. interrupt-parent = <&intc>;
  128. interrupts = <31 1>;
  129. reg-io-width = <1>;
  130. reg-shift = <2>;
  131. fifo-size = <1>;
  132. no-loopback-test;
  133. };
  134. uart1: uart@2100 {
  135. pinctrl-names = "default";
  136. pinctrl-0 = <&enable_uart1>;
  137. compatible = "ns16550a";
  138. reg = <0x2100 0x100>;
  139. clocks = <&ccu CLK_LXB>;
  140. interrupt-parent = <&intc>;
  141. interrupts = <30 2>;
  142. reg-io-width = <1>;
  143. reg-shift = <2>;
  144. fifo-size = <1>;
  145. no-loopback-test;
  146. status = "disabled";
  147. };
  148. gpio0: gpio-controller@3500 {
  149. compatible = "realtek,rtl8390-gpio", "realtek,otto-gpio";
  150. reg = <0x3500 0x20>;
  151. gpio-controller;
  152. #gpio-cells = <2>;
  153. ngpios = <24>;
  154. interrupt-controller;
  155. #interrupt-cells = <2>;
  156. interrupt-parent = <&intc>;
  157. interrupts = <23 2>;
  158. };
  159. watchdog0: watchdog@3150 {
  160. compatible = "realtek,rtl8390-wdt";
  161. reg = <0x3150 0xc>;
  162. realtek,reset-mode = "soc";
  163. clocks = <&ccu CLK_LXB>;
  164. timeout-sec = <30>;
  165. interrupt-parent = <&intc>;
  166. interrupt-names = "phase1", "phase2";
  167. interrupts = <19 4>, <18 4>;
  168. };
  169. };
  170. switchcore@1b000000 {
  171. compatible = "syscon", "simple-mfd";
  172. reg = <0x1b000000 0x10000>;
  173. #address-cells = <1>;
  174. #size-cells = <1>;
  175. ethernet0: ethernet {
  176. compatible = "realtek,rtl8392-eth";
  177. interrupt-parent = <&intc>;
  178. interrupts = <24 3>;
  179. #interrupt-cells = <1>;
  180. phy-mode = "internal";
  181. fixed-link {
  182. speed = <1000>;
  183. full-duplex;
  184. };
  185. };
  186. mdio_ctrl: mdio-controller {
  187. compatible = "realtek,rtl8392-mdio", "realtek,otto-mdio";
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. mdio_bus0: mdio-bus@0 {
  191. reg = <0>;
  192. #address-cells = <1>;
  193. #size-cells = <0>;
  194. };
  195. };
  196. mdio_aux: mdio-aux {
  197. compatible = "realtek,rtl8390-aux-mdio";
  198. #address-cells = <1>;
  199. #size-cells = <0>;
  200. status = "disabled";
  201. pinctrl-names = "default";
  202. pinctrl-0 = <&mdio_aux_mdx>;
  203. };
  204. mdio_serdes: mdio-serdes {
  205. compatible = "realtek,rtl8392-serdes-mdio", "realtek,otto-serdes-mdio";
  206. };
  207. pcs {
  208. compatible = "realtek,rtl8392-pcs", "realtek,otto-pcs";
  209. #address-cells = <1>;
  210. #size-cells = <0>;
  211. serdes0: serdes@0 {
  212. reg = <0>;
  213. };
  214. serdes1: serdes@1 {
  215. reg = <1>;
  216. };
  217. serdes2: serdes@2 {
  218. reg = <2>;
  219. };
  220. serdes3: serdes@3 {
  221. reg = <3>;
  222. };
  223. serdes4: serdes@4 {
  224. reg = <4>;
  225. };
  226. serdes5: serdes@5 {
  227. reg = <5>;
  228. };
  229. serdes6: serdes@6 {
  230. reg = <6>;
  231. };
  232. serdes7: serdes@7 {
  233. reg = <7>;
  234. };
  235. serdes8: serdes@8 {
  236. reg = <8>;
  237. };
  238. serdes9: serdes@9 {
  239. reg = <9>;
  240. };
  241. serdes10: serdes@10 {
  242. reg = <10>;
  243. };
  244. serdes11: serdes@11 {
  245. reg = <11>;
  246. };
  247. serdes12: serdes@12 {
  248. reg = <12>;
  249. };
  250. serdes13: serdes@13 {
  251. reg = <13>;
  252. };
  253. };
  254. soc_thermal: thermal {
  255. compatible = "realtek,rtl8390-thermal";
  256. #thermal-sensor-cells = <0>;
  257. };
  258. };
  259. pinmux@1b000004 {
  260. compatible = "pinctrl-single";
  261. reg = <0x1b000004 0x4>;
  262. pinctrl-single,bit-per-mux;
  263. pinctrl-single,register-width = <32>;
  264. pinctrl-single,function-mask = <0x1>;
  265. #pinctrl-cells = <2>;
  266. enable_uart1: pinmux_enable_uart1 {
  267. pinctrl-single,bits = <0x0 0x1 0x3>;
  268. };
  269. disable_jtag: pinmux_disable_jtag {
  270. pinctrl-single,bits = <0x0 0x2 0x3>;
  271. };
  272. };
  273. /* LED_GLB_CTRL */
  274. pinmux@1b0000e4 {
  275. compatible = "pinctrl-single";
  276. reg = <0x1b0000e4 0x4>;
  277. pinctrl-single,bit-per-mux;
  278. pinctrl-single,register-width = <32>;
  279. pinctrl-single,function-mask = <0x1>;
  280. #pinctrl-cells = <2>;
  281. /* enable GPIO 0 */
  282. pinmux_disable_sys_led: disable_sys_led {
  283. pinctrl-single,bits = <0x0 0x0 0x4000>;
  284. };
  285. /* enable AUX MDC/MDIO */
  286. mdio_aux_mdx: aux-mdx-pins {
  287. pinctrl-single,bits = <0x0 0x100000 0x1c0000>;
  288. };
  289. };
  290. sram0: sram@9f000000 {
  291. compatible = "mmio-sram";
  292. reg = <0x9f000000 0x18000>;
  293. #address-cells = <1>;
  294. #size-cells = <1>;
  295. ranges = <0 0x9f000000 0x18000>;
  296. };
  297. switch0: switch@1b000000 {
  298. status = "okay";
  299. compatible = "realtek,rtl83xx-switch";
  300. interrupt-parent = <&intc>;
  301. interrupts = <20 2>;
  302. };
  303. thermal_zones: thermal-zones {
  304. cpu-thermal {
  305. polling-delay-passive = <1000>;
  306. polling-delay = <1000>;
  307. coefficients = <1000 0>;
  308. thermal-sensors = <&soc_thermal>;
  309. trips {
  310. cpu-crit {
  311. temperature = <105000>;
  312. hysteresis = <2000>;
  313. type = "critical";
  314. };
  315. };
  316. };
  317. };
  318. };