en751221.dtsi 4.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. #include <dt-bindings/reset/econet,en751221-scu.h>
  3. /dts-v1/;
  4. / {
  5. compatible = "econet,en751221";
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. hpt_clock: clock {
  9. compatible = "fixed-clock";
  10. #clock-cells = <0>;
  11. clock-frequency = <200000000>; /* 200 MHz */
  12. };
  13. cpus: cpus {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. cpu@0 {
  17. device_type = "cpu";
  18. compatible = "mips,mips34Kc";
  19. reg = <0>;
  20. };
  21. };
  22. cpuintc: interrupt-controller {
  23. compatible = "mti,cpu-interrupt-controller";
  24. interrupt-controller;
  25. #address-cells = <0>;
  26. #interrupt-cells = <1>;
  27. };
  28. spi_ctrl: spi_controller@1fa10000 {
  29. compatible = "airoha,en7523-spi";
  30. reg = <0x1fa10000 0x140>;
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33. spi-rx-bus-width = <2>;
  34. spi-tx-bus-width = <2>;
  35. nand: nand@0 {
  36. compatible = "spi-nand";
  37. reg = <0>;
  38. nand-ecc-engine = <&nand>;
  39. };
  40. };
  41. chip_scu: syscon@1fa20000 {
  42. compatible = "econet,en751221-chip-scu", "syscon";
  43. reg = <0x1fa20000 0x388>;
  44. };
  45. intc: interrupt-controller@1fb40000 {
  46. compatible = "econet,en751221-intc";
  47. reg = <0x1fb40000 0x100>;
  48. interrupt-parent = <&cpuintc>;
  49. interrupts = <2>;
  50. interrupt-controller;
  51. #interrupt-cells = <1>;
  52. econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
  53. };
  54. scuclk: clock-controller@1fb00000 {
  55. compatible = "econet,en751221-scu", "syscon";
  56. reg = <0x1fb00000 0x970>;
  57. #clock-cells = <1>;
  58. #reset-cells = <1>;
  59. };
  60. ethernet: ethernet@1fb50000 {
  61. compatible = "econet,en751221-eth";
  62. reg = <0x1fb50000 0x10000>;
  63. resets = <&scuclk EN751221_FE_RST>,
  64. <&scuclk EN751221_FE_QDMA1_RST>,
  65. <&scuclk EN751221_FE_QDMA2_RST>,
  66. <&scuclk EN751221_GSW_RST>,
  67. <&scuclk EN751221_XPON_MAC_RST>,
  68. <&scuclk EN751221_XPON_PHY_RST>;
  69. reset-names = "fe", "qdma0", "qdma1", "gsw",
  70. "xpon-mac", "xpon-phy";
  71. #address-cells = <1>;
  72. #size-cells = <0>;
  73. interrupt-parent = <&intc>;
  74. interrupts = <21>, <22>;
  75. gmac0: mac@0 {
  76. compatible = "econet,eth-mac";
  77. reg = <0>;
  78. phy-mode = "trgmii";
  79. status = "disabled";
  80. fixed-link {
  81. speed = <1000>;
  82. full-duplex;
  83. pause;
  84. };
  85. };
  86. gmac1: mac@1 {
  87. compatible = "econet,eth-mac";
  88. reg = <1>;
  89. status = "disabled";
  90. phy-mode = "rgmii-rxid";
  91. };
  92. mdio: mdio-bus {
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. switch0: switch@1f {
  96. compatible = "mediatek,mt7530";
  97. #address-cells = <1>;
  98. #size-cells = <0>;
  99. reg = <0x1f>;
  100. mediatek,mcm;
  101. reset-names = "mcm";
  102. ports {
  103. #address-cells = <1>;
  104. #size-cells = <0>;
  105. reg = <0>;
  106. port@0 {
  107. status = "disabled";
  108. reg = <0>;
  109. label = "lan0";
  110. };
  111. port@1 {
  112. status = "disabled";
  113. reg = <1>;
  114. label = "lan1";
  115. };
  116. port@2 {
  117. status = "disabled";
  118. reg = <2>;
  119. label = "lan2";
  120. };
  121. port@3 {
  122. status = "disabled";
  123. reg = <3>;
  124. label = "lan3";
  125. };
  126. port@6 {
  127. reg = <6>;
  128. label = "cpu";
  129. ethernet = <&gmac0>;
  130. phy-mode = "trgmii";
  131. fixed-link {
  132. speed = <1000>;
  133. full-duplex;
  134. };
  135. };
  136. };
  137. };
  138. };
  139. };
  140. usb: usb@1fb90000 {
  141. compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
  142. reg = <0x1fb90000 0x4000>,
  143. <0x1fa80700 0x100>;
  144. reg-names = "mac", "ippc";
  145. #address-cells = <1>;
  146. #size-cells = <0>;
  147. interrupt-parent = <&intc>;
  148. interrupts = <17>;
  149. usb3-lpm-capable;
  150. };
  151. uart: serial@1fbf0000 {
  152. compatible = "ns16550";
  153. reg = <0x1fbf0000 0x30>;
  154. reg-io-width = <4>;
  155. reg-shift = <2>;
  156. interrupt-parent = <&intc>;
  157. interrupts = <0>;
  158. /*
  159. * Conversion of baud rate to clock frequency requires a
  160. * computation that is not in the ns16550 driver, so this
  161. * uart is fixed at 115200 baud.
  162. */
  163. clock-frequency = <1843200>;
  164. };
  165. timer_hpt: timer@1fbf0400 {
  166. compatible = "econet,en751221-timer";
  167. reg = <0x1fbf0400 0x100>;
  168. interrupt-parent = <&intc>;
  169. interrupts = <30>;
  170. clocks = <&hpt_clock>;
  171. };
  172. };