qcom-ipq4019-eap2200.dts 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/leds/common.h>
  6. / {
  7. model = "EnGenius EAP2200";
  8. compatible = "engenius,eap2200";
  9. aliases {
  10. led-boot = &led_power;
  11. led-failsafe = &led_power;
  12. led-running = &led_power;
  13. led-upgrade = &led_power;
  14. };
  15. keys {
  16. compatible = "gpio-keys";
  17. wps {
  18. label = "wps";
  19. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  20. linux,code = <KEY_WPS_BUTTON>;
  21. };
  22. };
  23. leds {
  24. compatible = "gpio-leds";
  25. led_power: power {
  26. function = LED_FUNCTION_POWER;
  27. color = <LED_COLOR_ID_AMBER>;
  28. gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
  29. };
  30. lan1 {
  31. label = "blue:lan1";
  32. gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
  33. };
  34. lan2 {
  35. label = "blue:lan2";
  36. gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
  37. };
  38. wlan2g {
  39. label = "blue:wlan2g";
  40. gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
  41. linux,default-trigger = "phy0tpt";
  42. };
  43. wlan5g {
  44. label = "yellow:wlan5g";
  45. gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
  46. linux,default-trigger = "phy1tpt";
  47. };
  48. wlan5g2 {
  49. label = "yellow:wlan5g2";
  50. gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
  51. linux,default-trigger = "phy2tpt";
  52. };
  53. mode {
  54. label = "blue:mode";
  55. gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
  56. };
  57. };
  58. };
  59. &watchdog {
  60. status = "okay";
  61. };
  62. &prng {
  63. status = "okay";
  64. };
  65. &crypto {
  66. status = "okay";
  67. };
  68. &blsp_dma {
  69. status = "okay";
  70. };
  71. &blsp1_spi1 {
  72. pinctrl-0 = <&spi_0_pins>;
  73. pinctrl-names = "default";
  74. status = "okay";
  75. cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
  76. flash@0 {
  77. compatible = "jedec,spi-nor";
  78. reg = <0>;
  79. spi-max-frequency = <24000000>;
  80. partitions {
  81. compatible = "fixed-partitions";
  82. #address-cells = <1>;
  83. #size-cells = <1>;
  84. partition0@0 {
  85. label = "0:SBL1";
  86. reg = <0x00000000 0x00040000>;
  87. read-only;
  88. };
  89. partition1@40000 {
  90. label = "0:MIBIB";
  91. reg = <0x00040000 0x00020000>;
  92. read-only;
  93. };
  94. partition2@60000 {
  95. label = "0:QSEE";
  96. reg = <0x00060000 0x00060000>;
  97. read-only;
  98. };
  99. partition3@c0000 {
  100. label = "0:CDT";
  101. reg = <0x000c0000 0x00010000>;
  102. read-only;
  103. };
  104. partition4@d0000 {
  105. label = "0:DDRPARAMS";
  106. reg = <0x000d0000 0x00010000>;
  107. read-only;
  108. };
  109. partition5@e0000 {
  110. label = "0:APPSBLENV";
  111. reg = <0x000e0000 0x00010000>;
  112. read-only;
  113. };
  114. partition6@f0000 {
  115. label = "0:APPSBL";
  116. reg = <0x000f0000 0x00080000>;
  117. read-only;
  118. };
  119. partition7@170000 {
  120. label = "0:ART";
  121. reg = <0x00170000 0x00010000>;
  122. read-only;
  123. nvmem-layout {
  124. compatible = "fixed-layout";
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. precal_art_1000: precal@1000 {
  128. reg = <0x1000 0x2f20>;
  129. };
  130. precal_art_5000: precal@5000 {
  131. reg = <0x5000 0x2f20>;
  132. };
  133. precal_art_9000: precal@9000 {
  134. reg = <0x9000 0x2f20>;
  135. };
  136. };
  137. };
  138. };
  139. };
  140. };
  141. &blsp1_uart1 {
  142. pinctrl-0 = <&serial_0_pins>;
  143. pinctrl-names = "default";
  144. status = "okay";
  145. };
  146. &cryptobam {
  147. status = "okay";
  148. };
  149. &nand {
  150. pinctrl-0 = <&nand_pins>;
  151. pinctrl-names = "default";
  152. status = "okay";
  153. nand@0 {
  154. partitions {
  155. compatible = "fixed-partitions";
  156. #address-cells = <1>;
  157. #size-cells = <1>;
  158. partition@0 {
  159. label = "rootfs1";
  160. reg = <0x00000000 0x04000000>;
  161. };
  162. partition@40000000 {
  163. label = "ubi";
  164. reg = <0x04000000 0x04000000>;
  165. };
  166. };
  167. };
  168. };
  169. &pcie0 {
  170. status = "okay";
  171. perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
  172. wake-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
  173. };
  174. &pcie_bridge0 {
  175. wifi@0,0 {
  176. compatible = "qcom,ath10k";
  177. reg = <0x00010000 0 0 0 0>;
  178. nvmem-cell-names = "pre-calibration";
  179. nvmem-cells = <&precal_art_9000>;
  180. ieee80211-freq-limit = <5470000 5875000>;
  181. qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
  182. };
  183. };
  184. &qpic_bam {
  185. status = "okay";
  186. };
  187. &tlmm {
  188. nand_pins: nand_pins {
  189. pullups {
  190. pins = "gpio53", "gpio58", "gpio59";
  191. function = "qpic";
  192. bias-pull-up;
  193. };
  194. pulldowns {
  195. pins = "gpio54", "gpio55", "gpio56",
  196. "gpio57", "gpio60", "gpio61",
  197. "gpio62", "gpio63", "gpio64",
  198. "gpio65", "gpio66", "gpio67",
  199. "gpio68", "gpio69";
  200. function = "qpic";
  201. bias-pull-down;
  202. };
  203. };
  204. serial_0_pins: serial_pinmux {
  205. mux {
  206. pins = "gpio16", "gpio17";
  207. function = "blsp_uart0";
  208. bias-disable;
  209. };
  210. };
  211. spi_0_pins: spi_0_pinmux {
  212. pinmux {
  213. function = "blsp_spi0";
  214. pins = "gpio13", "gpio14", "gpio15";
  215. drive-strength = <12>;
  216. bias-disable;
  217. };
  218. pinmux_cs {
  219. function = "gpio";
  220. pins = "gpio12";
  221. drive-strength = <2>;
  222. bias-disable;
  223. output-high;
  224. };
  225. };
  226. };
  227. &mdio {
  228. status = "okay";
  229. };
  230. &wifi0 {
  231. status = "okay";
  232. nvmem-cell-names = "pre-calibration";
  233. nvmem-cells = <&precal_art_1000>;
  234. qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
  235. };
  236. &wifi1 {
  237. status = "okay";
  238. ieee80211-freq-limit = <5170000 5350000>;
  239. nvmem-cell-names = "pre-calibration";
  240. nvmem-cells = <&precal_art_5000>;
  241. qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
  242. };