rtl838x.dtsi 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "macros.dtsi"
  3. #include <dt-bindings/clock/rtl83xx-clk.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. /dts-v1/;
  6. / {
  7. #address-cells = <1>;
  8. #size-cells = <1>;
  9. compatible = "realtek,rtl838x-soc";
  10. osc: oscillator {
  11. compatible = "fixed-clock";
  12. #clock-cells = <0>;
  13. clock-frequency = <25000000>;
  14. };
  15. ccu: clock-controller {
  16. compatible = "realtek,rtl8380-clock";
  17. #clock-cells = <1>;
  18. clocks = <&osc>;
  19. clock-names = "ref_clk";
  20. };
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. cpu@0 {
  25. compatible = "mips,mips4KEc";
  26. reg = <0>;
  27. clocks = <&ccu CLK_CPU>;
  28. operating-points-v2 = <&cpu_opp_table>;
  29. };
  30. };
  31. cpu_opp_table: opp-table-0 {
  32. compatible = "operating-points-v2";
  33. opp-shared;
  34. opp00 {
  35. opp-hz = /bits/ 64 <325000000>;
  36. };
  37. opp01 {
  38. opp-hz = /bits/ 64 <350000000>;
  39. };
  40. opp02 {
  41. opp-hz = /bits/ 64 <375000000>;
  42. };
  43. opp03 {
  44. opp-hz = /bits/ 64 <400000000>;
  45. };
  46. opp04 {
  47. opp-hz = /bits/ 64 <425000000>;
  48. };
  49. opp05 {
  50. opp-hz = /bits/ 64 <450000000>;
  51. };
  52. opp06 {
  53. opp-hz = /bits/ 64 <475000000>;
  54. };
  55. opp07 {
  56. opp-hz = /bits/ 64 <500000000>;
  57. };
  58. };
  59. aliases {
  60. serial0 = &uart0;
  61. serial1 = &uart1;
  62. mdio-gpio1 = &mdio_gpio;
  63. };
  64. chosen {
  65. bootargs = "earlycon";
  66. stdout-path = "serial0:115200n8";
  67. };
  68. cpuintc: cpuintc {
  69. compatible = "mti,cpu-interrupt-controller";
  70. #address-cells = <0>;
  71. #interrupt-cells = <1>;
  72. interrupt-controller;
  73. };
  74. /*
  75. * Provided for devices with RTL838xM SoC with revision A silicon.
  76. * Newer SoCs can use the &mdio_aux bus instead.
  77. */
  78. mdio_gpio: mdio {
  79. compatible = "virtual,mdio-gpio";
  80. #address-cells = <1>;
  81. #size-cells = <0>;
  82. gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>,
  83. <&gpio0 3 GPIO_ACTIVE_HIGH>;
  84. pinctrl-names = "default";
  85. pinctrl-0 = <&mdio_aux_gpio>;
  86. status = "disabled";
  87. };
  88. soc: soc {
  89. compatible = "simple-bus";
  90. #address-cells = <1>;
  91. #size-cells = <1>;
  92. ranges = <0x0 0x18000000 0x10000>;
  93. intc: interrupt-controller@3000 {
  94. compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
  95. reg = <0x3000 0x18>;
  96. interrupt-controller;
  97. #interrupt-cells = <2>;
  98. interrupt-parent = <&cpuintc>;
  99. interrupts = <2>, <3>, <4>, <5>, <6>;
  100. };
  101. spi0: spi@1200 {
  102. compatible = "realtek,rtl8380-spi";
  103. reg = <0x1200 0x100>;
  104. #address-cells = <1>;
  105. #size-cells = <0>;
  106. };
  107. timer0: timer@3100 {
  108. compatible = "realtek,rtl8380-timer", "realtek,otto-timer";
  109. reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
  110. <0x3130 0x10>, <0x3140 0x10>;
  111. interrupt-parent = <&intc>;
  112. interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
  113. clocks = <&ccu CLK_LXB>;
  114. };
  115. uart0: uart@2000 {
  116. compatible = "ns16550a";
  117. reg = <0x2000 0x100>;
  118. clocks = <&ccu CLK_LXB>;
  119. interrupt-parent = <&intc>;
  120. interrupts = <31 1>;
  121. reg-io-width = <1>;
  122. reg-shift = <2>;
  123. fifo-size = <1>;
  124. no-loopback-test;
  125. };
  126. uart1: uart@2100 {
  127. pinctrl-names = "default";
  128. pinctrl-0 = <&enable_uart1>;
  129. compatible = "ns16550a";
  130. reg = <0x2100 0x100>;
  131. clocks = <&ccu CLK_LXB>;
  132. interrupt-parent = <&intc>;
  133. interrupts = <30 0>;
  134. reg-io-width = <1>;
  135. reg-shift = <2>;
  136. fifo-size = <1>;
  137. no-loopback-test;
  138. status = "disabled";
  139. };
  140. watchdog0: watchdog@3150 {
  141. compatible = "realtek,rtl8380-wdt";
  142. reg = <0x3150 0xc>;
  143. realtek,reset-mode = "soc";
  144. clocks = <&ccu CLK_LXB>;
  145. timeout-sec = <30>;
  146. interrupt-parent = <&intc>;
  147. interrupt-names = "phase1", "phase2";
  148. interrupts = <19 3>, <18 4>;
  149. };
  150. gpio0: gpio-controller@3500 {
  151. compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
  152. reg = <0x3500 0x20>;
  153. gpio-controller;
  154. #gpio-cells = <2>;
  155. ngpios = <24>;
  156. interrupt-controller;
  157. #interrupt-cells = <2>;
  158. interrupt-parent = <&intc>;
  159. interrupts = <23 3>;
  160. };
  161. };
  162. switchcore@1b000000 {
  163. compatible = "syscon", "simple-mfd";
  164. reg = <0x1b000000 0x10000>;
  165. #address-cells = <1>;
  166. #size-cells = <1>;
  167. ethernet0: ethernet {
  168. compatible = "realtek,rtl8380-eth";
  169. interrupt-parent = <&intc>;
  170. interrupts = <24 3>;
  171. #interrupt-cells = <1>;
  172. phy-mode = "internal";
  173. fixed-link {
  174. speed = <1000>;
  175. full-duplex;
  176. };
  177. };
  178. mdio_ctrl: mdio-controller {
  179. compatible = "realtek,rtl8380-mdio", "realtek,otto-mdio";
  180. #address-cells = <1>;
  181. #size-cells = <0>;
  182. mdio_bus0: mdio-bus@0 {
  183. reg = <0>;
  184. #address-cells = <1>;
  185. #size-cells = <0>;
  186. };
  187. };
  188. mdio_aux: mdio-aux {
  189. compatible = "realtek,rtl8380-aux-mdio";
  190. #address-cells = <1>;
  191. #size-cells = <0>;
  192. status = "disabled";
  193. pinctrl-names = "default";
  194. pinctrl-0 = <&mdio_aux_mdx>, <&aux_mode_mdio>;
  195. };
  196. mdio_serdes: mdio-serdes {
  197. compatible = "realtek,rtl8380-serdes-mdio", "realtek,otto-serdes-mdio";
  198. };
  199. pcs {
  200. compatible = "realtek,rtl8380-pcs", "realtek,otto-pcs";
  201. #address-cells = <1>;
  202. #size-cells = <0>;
  203. serdes0: serdes@0 {
  204. reg = <0>;
  205. };
  206. serdes1: serdes@1 {
  207. reg = <1>;
  208. };
  209. serdes2: serdes@2 {
  210. reg = <2>;
  211. };
  212. serdes3: serdes@3 {
  213. reg = <3>;
  214. };
  215. serdes4: serdes@4 {
  216. reg = <4>;
  217. };
  218. serdes5: serdes@5 {
  219. reg = <5>;
  220. };
  221. };
  222. soc_thermal: thermal {
  223. compatible = "realtek,rtl8380-thermal";
  224. #thermal-sensor-cells = <0>;
  225. };
  226. };
  227. pinmux@1b000144 {
  228. compatible = "pinctrl-single";
  229. reg = <0x1b000144 0x4>;
  230. pinctrl-single,bit-per-mux;
  231. pinctrl-single,register-width = <32>;
  232. pinctrl-single,function-mask = <0x1>;
  233. #pinctrl-cells = <2>;
  234. /* I2C mode */
  235. aux_mode_i2c: i2c-pins {
  236. pinctrl-single,bits = <0x0 0x0 0x1>;
  237. };
  238. /* MDIO mode */
  239. aux_mode_mdio: mdx-pins {
  240. pinctrl-single,bits = <0x0 0x1 0x1>;
  241. };
  242. };
  243. pinmux: pinmux@1b001000 {
  244. compatible = "pinctrl-single";
  245. reg = <0x1b001000 0x4>;
  246. pinctrl-single,bit-per-mux;
  247. pinctrl-single,register-width = <32>;
  248. pinctrl-single,function-mask = <0x1>;
  249. #pinctrl-cells = <2>;
  250. enable_uart1: pinmux_enable_uart1 {
  251. pinctrl-single,bits = <0x0 0x10 0x10>;
  252. };
  253. };
  254. /* LED_GLB_CTRL */
  255. pinmux_led: pinmux@1b00a000 {
  256. compatible = "pinctrl-single";
  257. reg = <0x1b00a000 0x4>;
  258. pinctrl-single,bit-per-mux;
  259. pinctrl-single,register-width = <32>;
  260. pinctrl-single,function-mask = <0x1>;
  261. #pinctrl-cells = <2>;
  262. /* enable GPIO 0 */
  263. pinmux_disable_sys_led: disable_sys_led {
  264. pinctrl-single,bits = <0x0 0x0 0x8000>;
  265. };
  266. };
  267. pinmux@1b00a0e0 {
  268. compatible = "pinctrl-single";
  269. reg = <0x1b00a0e0 0x4>;
  270. pinctrl-single,bit-per-mux;
  271. pinctrl-single,register-width = <32>;
  272. pinctrl-single,function-mask = <0x1>;
  273. #pinctrl-cells = <2>;
  274. /* Use SoC GPIO 2/3 as GPIO */
  275. mdio_aux_gpio: gpio-pins {
  276. pinctrl-single,bits = <0x0 0x0 0x1>;
  277. };
  278. /* Use SoC GPIO 2/3 as MDC/MDIO */
  279. mdio_aux_mdx: mdx-pins {
  280. pinctrl-single,bits = <0x0 0x1 0x1>;
  281. };
  282. };
  283. sram0: sram@9f000000 {
  284. compatible = "mmio-sram";
  285. reg = <0x9f000000 0x10000>;
  286. #address-cells = <1>;
  287. #size-cells = <1>;
  288. ranges = <0 0x9f000000 0x10000>;
  289. };
  290. switch0: switch@1b000000 {
  291. compatible = "realtek,rtl8380-switch", "realtek,otto-switch";
  292. interrupt-parent = <&intc>;
  293. interrupts = <20 2>;
  294. };
  295. thermal_zones: thermal-zones {
  296. cpu-thermal {
  297. polling-delay-passive = <1000>;
  298. polling-delay = <1000>;
  299. coefficients = <1000 0>;
  300. thermal-sensors = <&soc_thermal>;
  301. trips {
  302. cpu-crit {
  303. temperature = <105000>;
  304. hysteresis = <2000>;
  305. type = "critical";
  306. };
  307. };
  308. };
  309. };
  310. };