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@@ -27,11 +27,105 @@
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spi0 = &spi0;
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};
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+ chosen {
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+ /*
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+ * not yet implemented.
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+ * stdout-path = &serial0 ":9600n8";
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+ * <https://www.spinics.net/lists/devicetree-compiler/msg02487.html>
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+ *
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+ * this should work... but it doesn't because CONFIG_CMDLINE in our
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+ * OpenWrt's target config sets "console=ttyS0,115200"
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+ * stdout-path = "/soc@ffe00000/serial@4500:9600n8";
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+ */
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+
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+ bootargs = "console=ttyS0,9600n8";
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+ };
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+
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+ cpus {
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+ PowerPC,P1020@0 {
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+ i-cache-sets = <0x80>;
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+ i-cache-size = <0x8000>;
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+ i-cache-block-size = <0x20>;
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+ d-cache-sets = <0x80>;
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+ d-cache-size = <0x8000>;
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+ d-cache-block-size = <0x20>;
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+ status = "okay";
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+ clock-frequency = <533333328>; /* 533.33 MHz */
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+ bus-frequency = <266666664>; /* 266.66 MHz */
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+ timebase-frequency = <33333333>; /* 33.33 MHz */
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+ };
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+
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+ PowerPC,P1020@1 {
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+ i-cache-sets = <0x80>;
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+ i-cache-size = <0x8000>;
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+ i-cache-block-size = <0x20>;
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+ d-cache-sets = <0x80>;
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+ d-cache-size = <0x8000>;
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+ d-cache-block-size = <0x20>;
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+ cpu-release-addr = <0x00 0xffff240>;
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+ enable-method = "spin-table";
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+ status = "disabled";
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+ clock-frequency = <533333328>;
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+ bus-frequency = <266666664>;
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+ timebase-frequency = <33333333>;
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+ };
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+ };
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+
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memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ reg = <0x00 0x00 0x00 0x10000000>;
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device_type = "memory";
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};
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+ /*
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+ * Usually, u-boot provided /memreserve/ properties by adding them during boot.
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+ * these have been converted to reserved-memory entries.
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+ */
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ /*
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+ * /memreserve/ 0x0000000000ffa000 0x0000000000004000;
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+ * The kernel complains when booting:
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+ *
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+ * | OF: fdt: Reserved memory: failed to reserve memory for node
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+ * 'firmware@ffa000': base 0x00ffa000, size 0 MiB
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+ *
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+ * But this likely uboot's bootargs + modified DTB. And if so, we don't care.
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+ * This is because we rely on our own dtb that's in the simpleImage.
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+ *
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+ * Note: This is backed up by u-boot. just before the kernel executes
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+ * it prints this final line:
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+ * | Loading Device Tree to 00ff9000, end 00fff1c4 ... OK
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+ *
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+ * firmware@ffa000 {
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+ * reg = <0x0 0xffa000 0x0 0x4000>;
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+ * no-map;
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+ * };
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+ */
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+
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+ // /memreserve/ 0x000000000fe2f000 0x0000000000000021;
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+ firmware@fe2f000 {
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+ reg = <0x0 0xfe2f000 0x0 0x21>;
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+ no-map;
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+ };
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+
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+ /*
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+ * /memreserve/ 0x000000000ffff000 0x0000000000001000;
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+ * that's the spin-table - see second CPU core binding.
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+ */
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+ firmware@ffff000 {
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+ reg = <0x0 0xffff000 0x0 0x1000>;
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+ no-map;
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+ };
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+ };
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+
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board_lbc: lbc: localbus@ffe05000 {
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+ bus-frequency = <16666666>; /* 16.66 MHz */
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reg = <0 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
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@@ -117,8 +211,12 @@
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board_soc: soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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+ bus-frequency = <266666664>;
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spi0: spi@7000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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temperature-sensor@1 {
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compatible = "ti,tmp125";
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reg = <1>;
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@@ -136,6 +234,9 @@
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compatible = "national,lp5521";
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reg = <0x32>;
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clock-mode = /bits/ 8 <2>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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#if 1
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led_fault_red: led@0 {
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reg = <0>;
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@@ -230,6 +331,9 @@
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};
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enet0: ethernet@b0000 {
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+ rx-stash-idx = <0x00>;
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+ rx-stash-len = <0x60>;
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+ bd-stash;
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status = "okay";
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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@@ -242,6 +346,9 @@
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};
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enet2: ethernet@b2000 {
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+ rx-stash-idx = <0x00>;
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+ rx-stash-len = <0x60>;
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+ bd-stash;
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status = "okay";
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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@@ -264,31 +371,22 @@
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pci0: pcie@ffe09000 {
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reg = <0x0 0xffe09000 0x0 0x1000>;
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- ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
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- 0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;
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+ ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>,
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+ <0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;
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pcie@0 {
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- ranges = <0x2000000 0x0 0xa0000000
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- 0x2000000 0x0 0xa0000000
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- 0x0 0x20000000
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-
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- 0x1000000 0x0 0x0
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- 0x1000000 0x0 0x0
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- 0x0 0x100000>;
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+ ranges = <0x2000000 0x0 0xa0000000 0x2000000 0x0 0xa0000000 0x0 0x20000000>,
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+ <0x1000000 0x0 0x00000000 0x1000000 0x0 0x00000000 0x0 0x00100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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reg = <0x0 0xffe0a000 0x0 0x1000>;
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- ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
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- 0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
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- pcie@0 {
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- ranges = <0x2000000 0x0 0xc0000000
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- 0x2000000 0x0 0xc0000000
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- 0x0 0x20000000
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+ ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>,
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+ <0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
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- 0x1000000 0x0 0x0
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- 0x1000000 0x0 0x0
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- 0x0 0x100000>;
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+ pcie@0 {
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+ ranges = <0x2000000 0x0 0xc0000000 0x2000000 0x0 0xc0000000 0x0 0x20000000>,
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+ <0x1000000 0x0 0x00000000 0x1000000 0x0 0x00000000 0x0 0x00100000>;
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};
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};
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@@ -302,7 +400,15 @@
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};
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};
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};
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+
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/include/ "fsl/p1020si-post.dtsi"
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+&serial0 {
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+ clock-frequency = <266666664>;
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+};
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+
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+&serial1 {
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+ clock-frequency = <266666664>;
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+};
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/*
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* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
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