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@@ -92,7 +92,49 @@
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if (!ath9k_hw_private_ops(ah)->restore_chainmask)
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--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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-@@ -1399,7 +1399,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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+@@ -491,6 +491,17 @@ static int __ath9k_hw_init(struct ath_hw
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+ if (ah->hw_version.devid == AR5416_AR9100_DEVID)
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+ ah->hw_version.macVersion = AR_SREV_VERSION_9100;
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+
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++ ath9k_hw_read_revisions(ah);
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++
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++ /*
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++ * Read back AR_WA into a permanent copy and set bits 14 and 17.
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++ * We need to do this to avoid RMW of this register. We cannot
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++ * read the reg when chip is asleep.
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++ */
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++ ah->WARegVal = REG_READ(ah, AR_WA);
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++ ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
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++ AR_WA_ASPM_TIMER_BASED_DISABLE);
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++
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+ if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
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+ ath_err(common, "Couldn't reset chip\n");
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+ return -EIO;
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+@@ -559,14 +570,6 @@ static int __ath9k_hw_init(struct ath_hw
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+
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+ ath9k_hw_init_mode_regs(ah);
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+
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+- /*
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+- * Read back AR_WA into a permanent copy and set bits 14 and 17.
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+- * We need to do this to avoid RMW of this register. We cannot
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+- * read the reg when chip is asleep.
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+- */
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+- ah->WARegVal = REG_READ(ah, AR_WA);
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+- ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
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+- AR_WA_ASPM_TIMER_BASED_DISABLE);
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+
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+ if (ah->is_pciexpress)
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+ ath9k_hw_configpcipowersave(ah, 0, 0);
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+@@ -1078,8 +1081,6 @@ static bool ath9k_hw_set_reset_power_on(
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+ return false;
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+ }
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+
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+- ath9k_hw_read_revisions(ah);
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+-
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+ return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
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+ }
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+
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+@@ -1399,7 +1400,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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ath9k_hw_init_qos(ah);
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if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
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