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@@ -57,8 +57,6 @@ Signed-off-by: Marek Behún <[email protected]>
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drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1351 ++++++++++++++++--
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1 file changed, 1234 insertions(+), 117 deletions(-)
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-diff --git a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
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-index dbb2d4308851..cbda47c33b98 100644
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--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
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+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
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@@ -5,12 +5,16 @@
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@@ -87,32 +85,6 @@ index dbb2d4308851..cbda47c33b98 100644
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+#include <linux/spinlock.h>
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-#define MVEBU_A3700_COMPHY_LANES 3
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--
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--/* COMPHY Fast SMC function identifiers */
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--#define COMPHY_SIP_POWER_ON 0x82000001
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--#define COMPHY_SIP_POWER_OFF 0x82000002
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--#define COMPHY_SIP_PLL_LOCK 0x82000003
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--
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--#define COMPHY_FW_MODE_SATA 0x1
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--#define COMPHY_FW_MODE_SGMII 0x2
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--#define COMPHY_FW_MODE_2500BASEX 0x3
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--#define COMPHY_FW_MODE_USB3H 0x4
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--#define COMPHY_FW_MODE_USB3D 0x5
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--#define COMPHY_FW_MODE_PCIE 0x6
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--#define COMPHY_FW_MODE_USB3 0xa
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--
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--#define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
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--#define COMPHY_FW_SPEED_2_5G 1
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--#define COMPHY_FW_SPEED_3_125G 2 /* 2500BASE-X */
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--#define COMPHY_FW_SPEED_5G 3
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--#define COMPHY_FW_SPEED_MAX 0x3F
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--
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--#define COMPHY_FW_MODE(mode) ((mode) << 12)
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--#define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \
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-- ((idx) << 8) | \
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-- ((speed) << 2))
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--#define COMPHY_FW_PCIE(mode, speed, width) (COMPHY_FW_NET(mode, 0, speed) | \
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-- ((width) << 18))
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+#define PLL_SET_DELAY_US 600
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+#define COMPHY_PLL_SLEEP 1000
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+#define COMPHY_PLL_TIMEOUT 150000
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@@ -267,7 +239,32 @@ index dbb2d4308851..cbda47c33b98 100644
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+ */
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+#define COMPHY_RESERVED_REG 0x0E
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+#define PHYCTRL_FRM_PIN_BIT BIT(13)
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-+
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+
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+-/* COMPHY Fast SMC function identifiers */
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+-#define COMPHY_SIP_POWER_ON 0x82000001
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+-#define COMPHY_SIP_POWER_OFF 0x82000002
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+-#define COMPHY_SIP_PLL_LOCK 0x82000003
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+-
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+-#define COMPHY_FW_MODE_SATA 0x1
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+-#define COMPHY_FW_MODE_SGMII 0x2
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+-#define COMPHY_FW_MODE_2500BASEX 0x3
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+-#define COMPHY_FW_MODE_USB3H 0x4
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+-#define COMPHY_FW_MODE_USB3D 0x5
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+-#define COMPHY_FW_MODE_PCIE 0x6
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+-#define COMPHY_FW_MODE_USB3 0xa
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+-
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+-#define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
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+-#define COMPHY_FW_SPEED_2_5G 1
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+-#define COMPHY_FW_SPEED_3_125G 2 /* 2500BASE-X */
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+-#define COMPHY_FW_SPEED_5G 3
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+-#define COMPHY_FW_SPEED_MAX 0x3F
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+-
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+-#define COMPHY_FW_MODE(mode) ((mode) << 12)
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+-#define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \
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+- ((idx) << 8) | \
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+- ((speed) << 2))
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+-#define COMPHY_FW_PCIE(mode, speed, width) (COMPHY_FW_NET(mode, 0, speed) | \
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+- ((width) << 18))
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+/* South Bridge PHY Configuration Registers */
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+#define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
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+
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@@ -385,10 +382,8 @@ index dbb2d4308851..cbda47c33b98 100644
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+ bool invert_tx;
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+ bool invert_rx;
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+ bool needs_reset;
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- };
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-
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--static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,
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-- unsigned long mode)
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++};
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++
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+struct gbe_phy_init_data_fix {
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+ u16 addr;
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+ u16 value;
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@@ -405,8 +400,10 @@ index dbb2d4308851..cbda47c33b98 100644
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+ { 0x0C3, 0x8000 }, { 0x0E2, 0x5550 }, { 0x0E3, 0x12A4 },
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+ { 0x0E4, 0x7D00 }, { 0x0E6, 0x0C83 }, { 0x101, 0xFCC0 },
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+ { 0x104, 0x0C10 }
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-+};
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-+
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+ };
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+
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+-static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,
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+- unsigned long mode)
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+/* 40M1G25 mode init data */
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+static u16 gbe_phy_init[512] = {
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+ /* 0 1 2 3 4 5 6 7 */
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@@ -479,25 +476,16 @@ index dbb2d4308851..cbda47c33b98 100644
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+};
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+
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+static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask)
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-+{
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-+ u32 val;
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-+
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-+ val = readl(addr);
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-+ val = (val & ~mask) | (data & mask);
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-+ writel(val, addr);
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-+}
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-+
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-+static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask)
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{
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- struct arm_smccc_res res;
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- s32 ret;
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-+ u16 val;
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++ u32 val;
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- arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
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- ret = res.a0;
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-+ val = readw(addr);
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++ val = readl(addr);
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+ val = (val & ~mask) | (data & mask);
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-+ writew(val, addr);
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++ writel(val, addr);
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+}
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- switch (ret) {
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@@ -505,6 +493,15 @@ index dbb2d4308851..cbda47c33b98 100644
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- return 0;
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- case SMCCC_RET_NOT_SUPPORTED:
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- return -EOPNOTSUPP;
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++static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask)
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++{
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++ u16 val;
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++
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++ val = readw(addr);
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++ val = (val & ~mask) | (data & mask);
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++ writew(val, addr);
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++}
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++
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+/* Used for accessing lane 2 registers (SATA/USB3 PHY) */
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+static void comphy_set_indirect(struct mvebu_a3700_comphy_priv *priv,
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+ u32 offset, u16 data, u16 mask)
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@@ -951,8 +948,9 @@ index dbb2d4308851..cbda47c33b98 100644
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+ }
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+
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+ return 0;
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-+}
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-+
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+ }
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+
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+-static int mvebu_a3700_comphy_get_fw_mode(int lane,
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+static int
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+mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane)
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+{
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@@ -1281,14 +1279,13 @@ index dbb2d4308851..cbda47c33b98 100644
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+ }
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+
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+ return 0;
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- }
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-
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--static int mvebu_a3700_comphy_get_fw_mode(int lane,
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++}
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++
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+static bool mvebu_a3700_comphy_check_mode(int lane,
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enum phy_mode mode,
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int submode)
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{
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-@@ -122,7 +1170,7 @@ static int mvebu_a3700_comphy_get_fw_mode(int lane,
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+@@ -122,7 +1170,7 @@ static int mvebu_a3700_comphy_get_fw_mod
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/* Unused PHY mux value is 0x0 */
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if (mode == PHY_MODE_INVALID)
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@@ -1297,7 +1294,7 @@ index dbb2d4308851..cbda47c33b98 100644
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for (i = 0; i < n; i++) {
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if (mvebu_a3700_comphy_modes[i].lane == lane &&
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-@@ -132,27 +1180,30 @@ static int mvebu_a3700_comphy_get_fw_mode(int lane,
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+@@ -132,27 +1180,30 @@ static int mvebu_a3700_comphy_get_fw_mod
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}
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if (i == n)
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@@ -1338,7 +1335,7 @@ index dbb2d4308851..cbda47c33b98 100644
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/* Just remember the mode, ->power_on() will do the real setup */
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lane->mode = mode;
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lane->submode = submode;
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-@@ -163,76 +1214,68 @@ static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
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+@@ -163,76 +1214,68 @@ static int mvebu_a3700_comphy_set_mode(s
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static int mvebu_a3700_comphy_power_on(struct phy *phy)
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{
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struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
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@@ -1450,7 +1447,7 @@ index dbb2d4308851..cbda47c33b98 100644
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.set_mode = mvebu_a3700_comphy_set_mode,
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.owner = THIS_MODULE,
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};
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-@@ -256,13 +1299,75 @@ static struct phy *mvebu_a3700_comphy_xlate(struct device *dev,
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+@@ -256,13 +1299,75 @@ static struct phy *mvebu_a3700_comphy_xl
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return ERR_PTR(-EINVAL);
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}
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@@ -1526,7 +1523,7 @@ index dbb2d4308851..cbda47c33b98 100644
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for_each_available_child_of_node(pdev->dev.of_node, child) {
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struct mvebu_a3700_comphy_lane *lane;
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-@@ -277,7 +1382,7 @@ static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
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+@@ -277,7 +1382,7 @@ static int mvebu_a3700_comphy_probe(stru
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continue;
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}
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@@ -1535,7 +1532,7 @@ index dbb2d4308851..cbda47c33b98 100644
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dev_err(&pdev->dev, "invalid 'reg' property\n");
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continue;
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}
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-@@ -295,11 +1400,21 @@ static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
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+@@ -295,11 +1400,21 @@ static int mvebu_a3700_comphy_probe(stru
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return PTR_ERR(phy);
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}
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@@ -1557,7 +1554,7 @@ index dbb2d4308851..cbda47c33b98 100644
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}
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provider = devm_of_phy_provider_register(&pdev->dev,
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-@@ -323,5 +1438,7 @@ static struct platform_driver mvebu_a3700_comphy_driver = {
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+@@ -323,5 +1438,7 @@ static struct platform_driver mvebu_a370
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module_platform_driver(mvebu_a3700_comphy_driver);
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MODULE_AUTHOR("Miquèl Raynal <[email protected]>");
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@@ -1565,6 +1562,3 @@ index dbb2d4308851..cbda47c33b98 100644
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+MODULE_AUTHOR("Marek Behún <[email protected]>");
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MODULE_DESCRIPTION("Common PHY driver for A3700");
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MODULE_LICENSE("GPL v2");
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---
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-2.34.1
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-
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