|
|
@@ -1,177 +0,0 @@
|
|
|
-From 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Mon Sep 17 00:00:00 2001
|
|
|
-From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
|
|
|
-Date: Fri, 14 May 2021 15:52:11 +0200
|
|
|
-Subject: [PATCH] fix(plat/marvell/a3720/uart): fix UART parent clock rate
|
|
|
- determination
|
|
|
-MIME-Version: 1.0
|
|
|
-Content-Type: text/plain; charset=UTF-8
|
|
|
-Content-Transfer-Encoding: 8bit
|
|
|
-
|
|
|
-The UART code for the A3K platform assumes that UART parent clock rate
|
|
|
-is always 25 MHz. This is incorrect, because the xtal clock can also run
|
|
|
-at 40 MHz (this is board specific).
|
|
|
-
|
|
|
-The frequency of the xtal clock is determined by a value on a strapping
|
|
|
-pin during SOC reset. The code to determine this frequency is already in
|
|
|
-A3K's comphy driver.
|
|
|
-
|
|
|
-Move the get_ref_clk() function from the comphy driver to a separate
|
|
|
-file and use it for UART parent clock rate determination.
|
|
|
-
|
|
|
-Signed-off-by: Pali Rohár <[email protected]>
|
|
|
-Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
|
|
|
----
|
|
|
- drivers/marvell/comphy/phy-comphy-3700.c | 24 +------------
|
|
|
- .../marvell/armada/a3k/common/plat_marvell.h | 2 ++
|
|
|
- .../marvell/armada/a3k/common/a3700_common.mk | 1 +
|
|
|
- .../armada/a3k/common/aarch64/a3700_clock.S | 35 +++++++++++++++++++
|
|
|
- .../armada/a3k/common/include/platform_def.h | 1 -
|
|
|
- .../armada/common/aarch64/marvell_helpers.S | 10 +++++-
|
|
|
- plat/marvell/armada/common/marvell_console.c | 1 +
|
|
|
- 7 files changed, 49 insertions(+), 25 deletions(-)
|
|
|
- create mode 100644 plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
|
|
|
-
|
|
|
---- a/drivers/marvell/comphy/phy-comphy-3700.c
|
|
|
-+++ b/drivers/marvell/comphy/phy-comphy-3700.c
|
|
|
-@@ -14,6 +14,7 @@
|
|
|
-
|
|
|
- #include <mvebu.h>
|
|
|
- #include <mvebu_def.h>
|
|
|
-+#include <plat_marvell.h>
|
|
|
-
|
|
|
- #include "phy-comphy-3700.h"
|
|
|
- #include "phy-comphy-common.h"
|
|
|
-@@ -29,15 +30,6 @@
|
|
|
- #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)
|
|
|
- #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)
|
|
|
-
|
|
|
--/*
|
|
|
-- * Below address in used only for reading, therefore no problem with concurrent
|
|
|
-- * Linux access.
|
|
|
-- */
|
|
|
--#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
|
|
|
-- #define MVEBU_XTAL_MODE_MASK BIT(9)
|
|
|
-- #define MVEBU_XTAL_MODE_OFFS 9
|
|
|
-- #define MVEBU_XTAL_CLOCK_25MHZ 0x0
|
|
|
--
|
|
|
- struct sgmii_phy_init_data_fix {
|
|
|
- uint16_t addr;
|
|
|
- uint16_t value;
|
|
|
-@@ -125,20 +117,6 @@ static uint16_t sgmii_phy_init[512] = {
|
|
|
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
|
|
|
- };
|
|
|
-
|
|
|
--/* returns reference clock in MHz (25 or 40) */
|
|
|
--static uint32_t get_ref_clk(void)
|
|
|
--{
|
|
|
-- uint32_t val;
|
|
|
--
|
|
|
-- val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
|
|
|
-- MVEBU_XTAL_MODE_OFFS;
|
|
|
--
|
|
|
-- if (val == MVEBU_XTAL_CLOCK_25MHZ)
|
|
|
-- return 25;
|
|
|
-- else
|
|
|
-- return 40;
|
|
|
--}
|
|
|
--
|
|
|
- /* PHY selector configures with corresponding modes */
|
|
|
- static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
|
|
|
- uint32_t comphy_mode)
|
|
|
---- a/include/plat/marvell/armada/a3k/common/plat_marvell.h
|
|
|
-+++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h
|
|
|
-@@ -100,4 +100,6 @@ void plat_marvell_interconnect_enter_coh
|
|
|
-
|
|
|
- const mmap_region_t *plat_marvell_get_mmap(void);
|
|
|
-
|
|
|
-+uint32_t get_ref_clk(void);
|
|
|
-+
|
|
|
- #endif /* PLAT_MARVELL_H */
|
|
|
---- a/plat/marvell/armada/a3k/common/a3700_common.mk
|
|
|
-+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
|
|
|
-@@ -38,6 +38,7 @@ PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/
|
|
|
- -I$/drivers/arm/gic/common/
|
|
|
-
|
|
|
- PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
|
|
|
-+ $(PLAT_COMMON_BASE)/aarch64/a3700_clock.S \
|
|
|
- $(MARVELL_DRV_BASE)/uart/a3700_console.S
|
|
|
-
|
|
|
- BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
|
|
|
---- /dev/null
|
|
|
-+++ b/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
|
|
|
-@@ -0,0 +1,35 @@
|
|
|
-+/*
|
|
|
-+ * Copyright (C) 2018 Marvell International Ltd.
|
|
|
-+ *
|
|
|
-+ * SPDX-License-Identifier: BSD-3-Clause
|
|
|
-+ * https://spdx.org/licenses
|
|
|
-+ */
|
|
|
-+
|
|
|
-+#include <asm_macros.S>
|
|
|
-+#include <platform_def.h>
|
|
|
-+
|
|
|
-+/*
|
|
|
-+ * Below address in used only for reading, therefore no problem with concurrent
|
|
|
-+ * Linux access.
|
|
|
-+ */
|
|
|
-+#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
|
|
|
-+ #define MVEBU_XTAL_MODE_MASK BIT(9)
|
|
|
-+
|
|
|
-+ /* -----------------------------------------------------
|
|
|
-+ * uint32_t get_ref_clk (void);
|
|
|
-+ *
|
|
|
-+ * returns reference clock in MHz (25 or 40)
|
|
|
-+ * -----------------------------------------------------
|
|
|
-+ */
|
|
|
-+.globl get_ref_clk
|
|
|
-+func get_ref_clk
|
|
|
-+ mov_imm x0, MVEBU_TEST_PIN_LATCH_N
|
|
|
-+ ldr w0, [x0]
|
|
|
-+ tst w0, #MVEBU_XTAL_MODE_MASK
|
|
|
-+ bne 40
|
|
|
-+ mov w0, #25
|
|
|
-+ ret
|
|
|
-+40:
|
|
|
-+ mov w0, #40
|
|
|
-+ ret
|
|
|
-+endfunc get_ref_clk
|
|
|
---- a/plat/marvell/armada/a3k/common/include/platform_def.h
|
|
|
-+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
|
|
|
-@@ -164,7 +164,6 @@
|
|
|
- * PL011 related constants
|
|
|
- */
|
|
|
- #define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x12000)
|
|
|
--#define PLAT_MARVELL_UART_CLK_IN_HZ 25000000
|
|
|
-
|
|
|
- #define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
|
|
|
- #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
|
|
|
---- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
|
|
|
-+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
|
|
|
-@@ -63,8 +63,16 @@ endfunc plat_marvell_calc_core_pos
|
|
|
- * ---------------------------------------------
|
|
|
- */
|
|
|
- func plat_crash_console_init
|
|
|
-- mov_imm x0, PLAT_MARVELL_UART_BASE
|
|
|
-+#ifdef PLAT_a3700
|
|
|
-+ mov x1, x30
|
|
|
-+ bl get_ref_clk
|
|
|
-+ mov x30, x1
|
|
|
-+ mov_imm x1, 1000000
|
|
|
-+ mul x1, x0, x1
|
|
|
-+#else
|
|
|
- mov_imm x1, PLAT_MARVELL_UART_CLK_IN_HZ
|
|
|
-+#endif
|
|
|
-+ mov_imm x0, PLAT_MARVELL_UART_BASE
|
|
|
- mov_imm x2, MARVELL_CONSOLE_BAUDRATE
|
|
|
- #ifdef PLAT_a3700
|
|
|
- b console_a3700_core_init
|
|
|
---- a/plat/marvell/armada/common/marvell_console.c
|
|
|
-+++ b/plat/marvell/armada/common/marvell_console.c
|
|
|
-@@ -14,6 +14,7 @@
|
|
|
-
|
|
|
- #ifdef PLAT_a3700
|
|
|
- #include <drivers/marvell/uart/a3700_console.h>
|
|
|
-+#define PLAT_MARVELL_UART_CLK_IN_HZ (get_ref_clk() * 1000000)
|
|
|
- #define console_marvell_register console_a3700_register
|
|
|
- #else
|
|
|
- #include <drivers/ti/uart/uart_16550.h>
|
Andre Heider